公开(公告)号：US20160291869A1

公开(公告)日：2016-10-06

申请号：US15007241

申请日：2016-01-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Ju YI ,  Seok Won AHN ,  Chan Ho YOON ,  Jung Pil LEE ,  Jun Ho CHOI

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688

Abstract: A data storage device includes a first scale-out controller configured to control a first non-volatile memory and a first volatile memory, a second scale-out controller configured to control a second non-volatile memory and a second volatile memory, and a controller configured to set a first memory management policy for the first non-volatile memory to be different from a second memory management policy for the second non-volatile memory.

Abstract translation: 数据存储装置包括配置成控制第一非易失性存储器和第一易失性存储器的第一横向扩展控制器，被配置为控制第二非易失性存储器和第二易失性存储器的第二横向扩展控制器，以及控制器 被配置为将第一非易失性存储器的第一存储器管理策略设置为不同于第二非易失性存储器的第二存储器管理策略。

公开(公告)号：US20150287471A1

公开(公告)日：2015-10-08

申请号：US14675847

申请日：2015-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Sung YU ,  Jung Pil LEE

IPC: G11C16/32

CPC classification number: G11C16/32 ,  G06F1/08 ,  G06F1/12 ,  G06F13/1689 ,  H03K5/05 ,  H03K5/06

Abstract: A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

Abstract translation: 根据本公开的示例性实施例的存储器控​​制器可以包括占空比调整电路，其响应于用于选通数据的时钟信号产生调整的时钟信号，以及选择电路，其输出时钟信号和经调整的时钟信号之一 作为输出时钟信号到存储器件。 每个经调整的时钟信号可以具有不同的占空比。