MEMORY CONTROLLER AND SYSTEM INCLUDING THE SAME
    2.
    发明申请
    MEMORY CONTROLLER AND SYSTEM INCLUDING THE SAME 有权
    内存控制器和系统,包括它们

    公开(公告)号:US20150287471A1

    公开(公告)日:2015-10-08

    申请号:US14675847

    申请日:2015-04-01

    Abstract: A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock signals in response to a clock signal for strobing data, and a selection circuit which outputs one of the clock signal and the adjusted clock signals to a memory device as an output clock signal. Each of the adjusted clock signals may have a different duty ratio.

    Abstract translation: 根据本公开的示例性实施例的存储器控​​制器可以包括占空比调整电路,其响应于用于选通数据的时钟信号产生调整的时钟信号,以及选择电路,其输出时钟信号和经调整的时钟信号之一 作为输出时钟信号到存储器件。 每个经调整的时钟信号可以具有不同的占空比。

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