公开(公告)号：US20210104452A1

公开(公告)日：2021-04-08

申请号：US16872567

申请日：2020-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  YOUNGBAE KIM ,  JI-YONG PARK

IPC: H01L23/498 ,  H05K1/11 ,  H01L29/768 ,  H01L23/31

Abstract: Disclosed are film packages and methods of fabricating package modules. The film package includes a film substrate that includes a chip region and a peripheral region facing each other in a first direction, a plurality of output pads that are arranged in the first direction on the chip region and on the peripheral region, and a semiconductor chip on the chip region and electrically connected to the output pads. The output pads on the chip region are arranged at regular first intervals along the first direction. The output pads include a plurality of first output pads that are arranged at a first pitch along the first direction on the chip region and a plurality of second output pads on the peripheral region. The second output pads are arranged at a second pitch greater than the first pitch of the first output pads.

公开(公告)号：US20240222348A1

公开(公告)日：2024-07-04

申请号：US18238099

申请日：2023-08-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol RYU ,  TAEHWAN KIM ,  SHLE-GE LEE

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L25/18 ,  H01L23/3128 ,  H01L23/5385 ,  H01L24/48 ,  H01L25/0652 ,  H10B80/00 ,  H01L2224/48091 ,  H01L2224/48227

Abstract: A semiconductor package may include a first package including a first substrate, a first semiconductor chip mounted on the first substrate, and a second substrate on the first semiconductor chip, the first package having a center region, a first edge region surrounding the center region, and a second edge region surrounding the first edge region in a plan view, dummy balls disposed on the center region and the second edge region of the first package, connection terminals disposed on the first edge region of the first package, and a second package including a third substrate disposed on the dummy balls and the connection terminals and a second semiconductor chip mounted on the third substrate. The dummy balls may be in contact with the second substrate and may be spaced apart from the third substrate, and the connection terminals may be coupled to the second and third substrates.

公开(公告)号：US20240203958A1

公开(公告)日：2024-06-20

申请号：US18352177

申请日：2023-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  HYUNGGIL BAEK ,  GYUNGHWAN OH

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0652 ,  H01L28/40 ,  H10B80/00 ,  H01L2224/16225

Abstract: A semiconductor package includes a lower substrate that has a contact region and a non-contact region, a first upper substrate on the lower substrate, a lower device on the first upper substrate, a plurality of first solder balls between the first upper substrate and the lower substrate contact region, a plurality of capacitors between the first upper substrate and the lower substrate non-contact region, and a plurality of support blocks between the plurality of capacitors and the lower substrate non-contact region.

公开(公告)号：US20210183724A1

公开(公告)日：2021-06-17

申请号：US16994938

申请日：2020-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SHLE-GE LEE ,  Youngbae Kim ,  AE-NEE JANG

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/528 ,  H01L23/00

Abstract: A semiconductor module includes a substrate having a central region, an outer region that surrounds the central region, and a middle region disposed between the central and the outer region, a first semiconductor package mounted on the central region of the substrate, a plurality of second semiconductor packages mounted on the middle region of the substrate, and a heat radiation structure disposed on the first semiconductor package and second semiconductor packages. The heat radiation structure includes a first part that is disposed on top surfaces of the first and second semiconductor packages, a second part that surrounds the middle region, a third part that is spaced apart from the second part and surrounds the first semiconductor package, and a fourth part that connects the second part to the third part.