公开(公告)号：US20240363464A1

公开(公告)日：2024-10-31

申请号：US18767895

申请日：2024-07-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Hsuan Tai ,  Chih-Hua Chen ,  Hao-Yi Tsai ,  Yu-Chih Huang ,  Chia-Hung Liu ,  Ting-Ting Kuo

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/66 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/522 ,  H01L23/532 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L22/20 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/82 ,  H01L24/92 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/83005 ,  H01L2224/83101 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: A package structure is provided. The package structure includes a die, an encapsulant, a first redistribution line (RDL) structure, a second RDL structure, and a through via. The encapsulant laterally encapsulates the die. The first redistribution line (RDL) structure on a first side of the die and the encapsulant, wherein the first RDL structure comprises a dielectric layer and a redistribution layer in the dielectric layer. The second RDL structure is located on a second side of the die and the encapsulant. The through via extends through the encapsulant and the first redistribution line structure and connecting the second RDL structure. The through via is laterally separated from the redistribution layer by the dielectric layer therebetween.

公开(公告)号：US20240363365A1

公开(公告)日：2024-10-31

申请号：US18769434

申请日：2024-07-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Hui Cheng ,  Szu-Wei Lu ,  Ping-Yin Hsieh ,  Chih-Hao Chen

IPC: H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L21/486 ,  H01L21/561 ,  H01L24/24 ,  H01L24/25 ,  H01L24/96 ,  H01L25/105 ,  H01L2224/24175 ,  H01L2224/25171 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a semiconductor die, conductive through vias, an insulating encapsulant, and a redistribution structure. The conductive through vias are electrically coupled to the semiconductor die. The insulating encapsulant laterally encapsulates the semiconductor die and the conductive through vias, wherein the insulating encapsulant has a recess ring surrounding the semiconductor die, the conductive through vias are located under the recess ring, and a vertical projection of each of the conductive through vias overlaps with a vertical projection of the recess ring. The redistribution structure is electrically connected to the semiconductor die and the conductive through vias.

公开(公告)号：US20240355794A1

公开(公告)日：2024-10-24

申请号：US18497039

申请日：2023-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choongbin Yim ,  Jongkook Kim ,  Chengtar Wu

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H10B80/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/565 ,  H01L23/3135 ,  H01L23/3738 ,  H01L23/49822 ,  H01L23/49894 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H10B80/00 ,  H01L24/83 ,  H01L2224/08145 ,  H01L2224/08235 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83862 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/1436 ,  H01L2924/15153 ,  H01L2924/3511

Abstract: A semiconductor package may include: a redistribution layer structure; a semiconductor structure on the redistribution layer structure; a printed circuit board on the redistribution layer structure and extending around a side surface of the semiconductor structure; a molding material extending around the semiconductor structure on the redistribution layer structure; and a silicon interposer on the printed circuit board and the molding material.

公开(公告)号：US20240347434A1

公开(公告)日：2024-10-17

申请号：US18599878

申请日：2024-03-08

Applicant: NEPES CO., LTD. ,  NEPES LAWEH CORPORATION

Inventor： Jong Heon KIM ,  Young Ho KIM ,  Yun Mook PARK ,  Young Mo LEE ,  Hyung Jin SHIN ,  Kyu Shik KIM ,  Bo Mi LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1005

Abstract: A package for semiconductor is disclosed. The semiconductor package according to an aspect of the present invention may include a semiconductor chip; a first insulating layer for embedding the semiconductor chip and protecting the semiconductor chip; a redistribution layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer and for embedding the redistribution layer and protecting the redistribution layer; and a conductive pad disposed on the second insulating layer.

公开(公告)号：US12119338B2

公开(公告)日：2024-10-15

申请号：US18447655

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen

IPC: H01L21/44 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L23/00 ,  H01L23/12 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L23/544 ,  H01L23/58 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/12 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/544 ,  H01L23/562 ,  H01L23/585 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L24/32 ,  H01L24/48 ,  H01L25/105 ,  H01L2221/68372 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/2518 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/18165 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/15311 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2924/00014 ,  H01L2224/85399

Abstract: Semiconductor device packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region and a molding material disposed around the integrated circuit die mounting region. An interconnect structure is disposed over the molding material and the integrated circuit die mounting region. A protection pattern is disposed in a perimeter region of the package. The protection pattern includes a conductive feature.

公开(公告)号：US12119306B2

公开(公告)日：2024-10-15

申请号：US18307277

申请日：2023-04-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Gyuho Kang ,  Un-Byoung Kang ,  Byeongchan Kim ,  Junyoung Park ,  Jongho Lee ,  Hyunsu Hwang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10

CPC classification number: H01L23/5389 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L25/105 ,  H01L2224/16225

Abstract: A semiconductor package including a redistribution substrate including an insulating layer and redistribution patterns in the insulating layer may be provided. Each of the redistribution patterns may include a via portion, a pad portion vertically overlapping the via portion, and a line portion extending from the pad portion. The via portion, the pad portion, and the line portion may be connected to each other to form a single object. A level of a bottom surface of the pad portion may be lower than a level of a bottom surface of the line portion. A width of the line portion may have a largest value at a level between a top surface of the line portion and the bottom surface of the line portion.

公开(公告)号：US20240339385A1

公开(公告)日：2024-10-10

申请号：US18626080

申请日：2024-04-03

Applicant: NEPES LAWEH CORPORATION ,  nepes hayyim

Inventor： Byungcheol Kim ,  Mary Maye Melgo

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49575 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/49517 ,  H01L23/49541 ,  H01L24/16 ,  H01L24/20 ,  H01L24/32 ,  H01L24/83 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/21 ,  H01L2224/32245 ,  H01L2224/83

Abstract: A semiconductor package according to an embodiment includes frames; a first semiconductor device disposed on the frames; at least one conductive post disposed on the frames and laterally spaced apart from the first semiconductor device; an encapsulation member surrounding the first semiconductor device and the conductive post; and a redistribution layer disposed on the encapsulation member and electrically connected to the first semiconductor device and the conductive post.

公开(公告)号：US12113027B2

公开(公告)日：2024-10-08

申请号：US18341788

申请日：2023-06-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Yu Lu ,  Ping-Kang Huang ,  Sao-Ling Chiu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/49816 ,  H01L23/5385 ,  H01L25/105 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16235

Abstract: Board substrates, three-dimensional integrated circuit structures and methods of forming the same are disclosed. A board substrate includes a core layer, a first build-up layer, a second build-up layer, a first group of bumps, a second first group of bumps and at least one first underfill blocking wall. The first build-up layer and the second build-up layer are disposed on opposite sides of the core layer. The first group of bumps is disposed over the first build-up layer. The second first group of bumps is disposed over the first build-up layer. The at least one first underfill blocking wall is disposed over the first build-up layer and between the first group of bumps and the second group of bumps.

公开(公告)号：US20240332268A1

公开(公告)日：2024-10-03

申请号：US18739690

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： KYOUNG LIM SUK ,  SEOKHYUN LEE

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L24/09 ,  H01L24/16 ,  H01L24/17 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0231 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/08235 ,  H01L2224/16227 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A method of fabricating a semiconductor package includes providing a semiconductor chip, forming a redistribution substrate, and fabricating a package including the semiconductor chip disposed on the redistribution substrate. The forming of the redistribution substrate may include forming a first insulating layer on a substrate, the first insulating layer having a first opening formed therein, forming an integrally formed first redistribution pattern in the first opening and on the first insulating layer, forming a second insulating layer on the first insulating layer to cover the first redistribution pattern, and performing a planarization process on the second insulating layer to expose the first redistribution pattern.

公开(公告)号：US20240321840A1

公开(公告)日：2024-09-26

申请号：US18596240

申请日：2024-03-05

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Jingfan YANG ,  Peng Zhang

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/13 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: A three-dimensional semiconductor package including: a package substrate having a first surface and a second surface opposite to the first surface; a first redistribution layer on the first surface of the package substrate, the first redistribution layer having a first surface and a second surface opposite to each other; a first chip on the first surface of the first redistribution layer, electrically connected to the first redistribution layer, and including first through silicon vias; first connection terminals electrically connected to one ends of the first through silicon vias; a second redistribution layer on the second surface of the package substrate, the second redistribution layer having a first surface and a second surface opposite to each other, the first surface of the second redistribution layer facing the second surface of the package substrate; and a second chip on the second surface of the second redistribution layer.