公开(公告)号：US20200092989A1

公开(公告)日：2020-03-19

申请号：US16689403

申请日：2019-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shle-Ge LEE ,  Youngbae KIM

IPC: H05K1/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498

Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.

公开(公告)号：US20250022772A1

公开(公告)日：2025-01-16

申请号：US18425010

申请日：2024-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Insik HAN ,  Shle-Ge LEE ,  Junho LEE ,  WanSun KIM

IPC: H01L23/40 ,  H01L23/00 ,  H01L23/522 ,  H01L25/18 ,  H10B80/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a package substrate. A chip structure is on the package substrate. A stiffener covers the chip structure and the package substrate. Screws fix the stiffener to the package substrate. The stiffener includes a main portion that covers an upper surface of the chip structure. A vertical portion that covers lateral side surfaces of the chip structure. The vertical portion extends from an end of the main portion. An edge portion extending laterally from the vertical portion and covering the upper surface of the package substrate. The screws penetrate the edge portion and the package substrate and couple the edge portion to the package substrate.

公开(公告)号：US20240234274A1

公开(公告)日：2024-07-11

申请号：US18372257

申请日：2023-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tong Suk KIM ,  Sang Woong LEE ,  Shle-Ge LEE ,  Seung Soo HA ,  Chang Ui HONG

IPC: H01L23/498 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L23/49816 ,  H01L23/49838 ,  H01L25/0655 ,  H01L25/105 ,  H01L24/16 ,  H01L2224/16225

Abstract: A semiconductor package, including a first structure including a ball array region on a lower surface of the first structure and an external region completely surrounding the ball array region, the ball array region including a passive element region in which solder balls are not disposed and an edge region completely surrounding the passive element region, a first semiconductor chip on an upper surface of the first structure, a passive element in the passive element region on the lower surface of the first structure, the passive element not in the edge region on the lower surface of the first structure, and a first ball array in the edge region on the lower surface of the first structure, the first ball array including two or more first power solder balls supplying power to at least one of the passive element and the first semiconductor chip.