公开(公告)号：US20230267190A1

公开(公告)日：2023-08-24

申请号：US18083881

申请日：2022-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heangsu KIM ,  Yeongseon KIM ,  Ilwoo KIM ,  Sungmin AHN

IPC: G06F21/34 ,  G06F21/60

CPC classification number: G06F21/34 ,  G06F21/602

Abstract: A method for operating an electronic device including at least one communication circuit and a display include receiving, via a connection from another electronic device, data that is encrypted based on scan of the barcode through a camera of the other electronic device. The method include executing the initial setup based on at least one signal received from the other electronic device after authenticating the other electronic device by using the data.

公开(公告)号：US20230138813A1

公开(公告)日：2023-05-04

申请号：US17978507

申请日：2022-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Chajea JO ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.

公开(公告)号：US20250105127A1

公开(公告)日：2025-03-27

申请号：US18659864

申请日：2024-05-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dohyun KIM ,  Yeongseon KIM ,  JUHYEON KIM ,  HYOEUN KIM ,  SUNKYOUNG SEO ,  Haksun LEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L23/544 ,  H01L25/10

Abstract: A semiconductor package may include a first dielectric structure, a first pad in the first dielectric structure, a first semiconductor chip provided on the first dielectric structure, and a bump electrically connected to the first pad. The first semiconductor chip includes: a first substrate; a first chip dielectric layer in contact with the first dielectric structure; and a first chip pad in contact with a top surface of the first pad. The first pad may be provided between the bump and the first chip of the first semiconductor chip. The first pad may include a first conductive layer and a second conductive layer covered by the first conductive layer. The bump may be positioned closer to the first conductive layer than to the second conductive layer.

公开(公告)号：US20250105097A1

公开(公告)日：2025-03-27

申请号：US18670378

申请日：2024-05-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeongseon KIM ,  JUHYEON KIM

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/28 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package includes a first chip, a second chip on an active surface of the first chip, a dummy chip on the active surface of the first chip, a mold layer on the active surface of the first chip and enclosing the second chip and the dummy chip, and a conductive post vertically penetrating the mold layer proximate to the second chip and the dummy chip to be coupled to the active surface of the first chip. An active surface of the second chip and an active surface of the dummy chip may be in direct contact with the active surface of the first chip. The dummy chip may include a first via. The second chip includes a second via chip. A width of the first via is larger than a width of the second via.

公开(公告)号：US20240290669A1

公开(公告)日：2024-08-29

申请号：US18385082

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Dohyun KIM ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM ,  Jeongoh HA

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L22/32 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/1436

Abstract: A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.