公开(公告)号：US20240063193A1

公开(公告)日：2024-02-22

申请号：US18210958

申请日：2023-06-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungdon MUN ,  Juhyeon KIM ,  Sangcheon PARK ,  Taeyoung LEE

IPC: H01L25/10 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/105 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/80 ,  H01L2224/08145 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/8082 ,  H01L2924/1436 ,  H01L2924/1432

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate having a first active surface and a first inactive surface opposite to each other, a plurality of through electrodes penetrating the first semiconductor substrate, and a rear cover layer covering the first inactive surface, a second semiconductor chip stacked on the first semiconductor chip and including a second semiconductor substrate having a second active surface and a second inactive surface opposite to each other, and a front cover layer covering the second active surface, a plurality of signal pad structures penetrating the rear cover layer and the front cover layer to be electrically connected to the plurality of through electrodes, and a plurality of dummy pad structures apart from the plurality of signal pad structures in a horizontal direction, and penetrating the rear cover layer and the front cover layer.

公开(公告)号：US20240290669A1

公开(公告)日：2024-08-29

申请号：US18385082

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Dohyun KIM ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM ,  Jeongoh HA

IPC: H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L22/32 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L2924/1436

Abstract: A semiconductor structure according to an embodiment may include: an interconnect structure on a substrate; an interlayer dielectric layer on the interconnect structure; a first conductive pad within the interlayer dielectric layer and electrically coupled with the interconnect structure; a second conductive pad within the interlayer dielectric layer and electrically decoupled from the interconnect structure; a first via plug within the interlayer dielectric layer; and a bonding structure on the interlayer dielectric layer and including a first bonding pad, a plurality of second bonding pads, and a bonding dielectric layer, wherein the first bonding pad is electrically coupled to the first via plug, some of the plurality of second bonding pads are spaced apart from the first conductive pad in a vertical direction, and others of the plurality of second bonding pads are spaced apart from the second conductive pad in the vertical direction.

公开(公告)号：US20240355780A1

公开(公告)日：2024-10-24

申请号：US18387707

申请日：2023-11-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Juhyeon KIM ,  Chajea JO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/08 ,  H01L2224/08146 ,  H01L2924/181

Abstract: Semiconductor packages and fabrication methods thereof are provided. A semiconductor package includes first and second structures. The first structure includes: a first semiconductor substrate that has an active surface on which a first semiconductor device is configured to be provided, and an inactive surface opposite to the active surface; a first through via that vertically penetrates the first semiconductor substrate and protrudes from the inactive surface of the first semiconductor substrate; a first protection layer that covers the inactive surface of the first semiconductor substrate and buries the first through via; and a first pad that penetrates at least a portion of the first protection layer and is coupled to the first through via. The second structure includes a second pad, the first structure and the second structure are bonded to each other, and the first pad and the second pad are in contact with each other.

公开(公告)号：US20230138813A1

公开(公告)日：2023-05-04

申请号：US17978507

申请日：2022-11-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunkyoung SEO ,  Chajea JO ,  Yeongseon KIM ,  Juhyeon KIM ,  Hyoeun KIM

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A first semiconductor chip includes a first semiconductor substrate, a first wiring structure arranged on the first semiconductor substrate, a plurality of through electrodes penetrating through at least a portion of the first semiconductor substrate, and a plurality of first bonding pads respectively connected to the plurality of through electrodes. A second semiconductor chip is stacked on the first semiconductor chip and includes a second semiconductor substrate, a second wiring structure arranged on the second semiconductor substrate, and a second bonding pad connected to each of the plurality of first bonding pads and arranged on the active surface of the second semiconductor substrate. Each first bonding pad has a top surface that is in direct contact with the second bonding pad and a bottom surface that is in direct contact with one through electrode.