公开(公告)号：US20210303395A1

公开(公告)日：2021-09-30

申请号：US17344180

申请日：2021-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Hyun KIM ,  Yong-Gyu CHU ,  Jun Jin KONG ,  Ki-Jun LEE ,  Myung-Kyu LEE

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  G11C11/401 ,  H01L25/065

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.

公开(公告)号：US20190340067A1

公开(公告)日：2019-11-07

申请号：US16217249

申请日：2018-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-HYUN KIM ,  Yong-Gyu CHU ,  Jun Jin KONG ,  Ki-Jun LEE ,  Myung-Kyu LEE

IPC: G06F11/10 ,  G11C29/52 ,  G06F13/16 ,  H01L25/065 ,  G11C11/401

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of memory cells; an error correction code (ECC) engine configured to detect and/or correct at least one error bit in read data and configured to generate a decoding status flag indicative of whether the at least one error bit is detected and/or corrected, wherein the read data is read from the memory cell array; a channel interface circuit configured to receive the read data and the decoding status flag from the ECC engine and configured to transmit the read data and the decoding status flag to a memory controller, wherein the channel interface circuit is configured to transmit the decoding status flag to the memory controller through a pin; and a control logic circuit configured to control the ECC engine and the channel interface circuit in response to an address and a command from the memory controller.