公开(公告)号：US12189830B2

公开(公告)日：2025-01-07

申请号：US17847593

申请日：2022-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bohdan Karpinskyy ,  Yong-ki Lee ,  Ji-eun Park ,  Kyoung-moon Ahn ,  Yun-hyeok Choi

IPC: G06F21/75 ,  G06F21/56 ,  G06F21/72 ,  H01L23/00 ,  H03K19/173 ,  H04L9/08 ,  H03K19/21

Abstract: An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality of PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.

公开(公告)号：US20200210628A1

公开(公告)日：2020-07-02

申请号：US16553318

申请日：2019-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BOHDAN KARPINSKYY ,  Yong-ki Lee ,  Ji-eun Park ,  Kyoung-moon Ahn ,  Yun-hyeok Choi

IPC: G06F21/75 ,  H01L23/00 ,  H03K19/173 ,  G06F21/72 ,  G06F21/56

Abstract: An integrated circuit including: a plurality of physically unclonable function (PUF) cells each configured to generate a cell signal having a unique value; a selector configured to output a first signal obtained by not inverting a cell signal output by a PUF cell selected from the plurality PUF cells and a second signal obtained by inverting the cell signal; and a key generator configured to generate a security key in response to the first signal or the second signal, wherein the selector includes a first conversion circuit configured to generate the first signal and a second conversion circuit having the same structure as the first conversion circuit and configured to generate the second signal.

公开(公告)号：US11561769B2

公开(公告)日：2023-01-24

申请号：US16541705

申请日：2019-08-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-eun Park ,  Yong-ki Lee ,  Yun-hyeok Choi ,  Bohdan Karpinskyy

IPC: G06F7/58 ,  H03K3/017 ,  H03K19/21 ,  H03K3/03

Abstract: A random number generator including: a first ring oscillator including a first inverter chain, the first inverter chain including a plurality of serially connected first inverters, the first ring oscillator configured to output a first random signal generated at a first sub-node between two neighboring first inverters among the plurality of first inverters; a second ring oscillator including a second inverter chain, the second inverter chain including a plurality of serially connected second inverters, the second ring oscillator configured to output a second random signal generated at a second sub-node between two neighboring second inverters among the plurality of second inverters; and a signal processing circuit for generating a random number by combining the first random signal with the second random signal.

公开(公告)号：US10243749B2

公开(公告)日：2019-03-26

申请号：US15871306

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-wook Park ,  Dae-hyeon Kim ,  Mi-jung Noh ,  Bohdan Karpinskyy ,  Yong-ki Lee ,  Yun-hyeok Choi

IPC: H04L9/32 ,  H04L9/08 ,  H03K19/003

Abstract: A physical unclonable function (PUF) circuit and a PUF system including the same are provided. The PUF circuit includes a plurality of PUF cells each configured to generate an output voltage by dividing a power voltage, a reference voltage generator configured to generate a first reference voltage by dividing the power voltage, and a comparing unit configured to sequentially compare the output voltages of the plurality of PUF cells with the first reference voltage to output data values of the plurality of PUF cells.

公开(公告)号：US20180337793A1

公开(公告)日：2018-11-22

申请号：US15871306

申请日：2018-01-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-wook Park ,  Dae-hyeon Kim ,  Mi-jung Noh ,  Bohdan Karpinskyy ,  Yong-ki Lee ,  Yun-hyeok Choi

IPC: H04L9/32 ,  H03K19/003 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H03K19/003 ,  H04L9/0866

Abstract: A physical unclonable function (PUF) circuit and a PUF system including the same are provided. The PUF circuit includes a plurality of PUF cells each configured to generate an output voltage by dividing a power voltage, a reference voltage generator configured to generate a first reference voltage by dividing the power voltage, and a comparing unit configured to sequentially compare the output voltages of the plurality of PUF cells with the first reference voltage to output data values of the plurality of PUF cells.

公开(公告)号：US10439613B2

公开(公告)日：2019-10-08

申请号：US16004517

申请日：2018-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Bohdan Karpinskyy ,  Dae-hyeon Kim ,  Mi-jung Noh ,  Sang-wook Park ,  Yong-ki Lee ,  Yun-hyeok Choi

IPC: H03K19/00 ,  H04L9/08 ,  G06F7/58 ,  H03K19/003 ,  H01L23/00 ,  H04L9/32

Abstract: An integrated circuit for a physically unclonable function (PUF) includes first and second PUF cells and a combination circuit. The first and second PUF cells respectively output first and second cell signals having unique levels based on a threshold level of a logic gate. The combination circuit includes a first stage that generates a first combination signal based on the first and second cell signals. The first and second PUF cells respectively include first and second logic gates to respectively output the first and second cell signals. The combination circuit includes a third logic gate that receives the first and second cell signals and outputs the first combination signal. The third logic gate has a same structure as each of the first and second logic gates.

公开(公告)号：US10146507B2

公开(公告)日：2018-12-04

申请号：US15404826

申请日：2017-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Karpinskyy Bohdan ,  Yong-ki Lee ,  Mi-jung Noh ,  Sang-wook Park ,  Kitak Kim ,  Yong-Soo Kim ,  Yun-hyeok Choi

IPC: G06F7/58

Abstract: An apparatus for testing a random number generator includes a correlation test circuit and a randomness determination circuit. The correlation test circuit extracts a first plurality of bit pairs each including two bits spaced apart from each other by a first distance in a bit stream generated by the random number generator, obtains a first sum of differences between respective two bits of the first plurality of bit pairs, and obtains a second sum of differences between respective two bits of a second plurality of bit pairs, the second plurality of bit pairs each including two bits spaced apart from each other by a second distance, different from the first distance, in the bit stream. The randomness determination circuit determines a randomness of the bit stream, based on the first sum and the second sum.