公开(公告)号：US20140376305A1

公开(公告)日：2014-12-25

申请号：US14369651

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: G11C11/419 ,  H01L27/11

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

Abstract: The present invention discloses a circuit for improving process robustness of sub-threshold SRAM memory cells, which serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to the PMOS tube of the sub-threshold SRAM memory cell and the substrate of a PMOS tube in the circuit. The circuit comprises a detection circuit for threshold voltage of PMOS tube and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS tubes in the sub-threshold SRAM memory cell and the substrate voltage of the PMOS tube in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS tubes and NMOS tubes resulted from process fluctuations and thereby regulate the threshold voltages of the PMOS tubes, so that the threshold voltage of PMOS tubes matches the threshold voltage of NMOS tubes. The circuit improves the noise margin of sub-threshold SRAM memory cells and effectively improves the process robustness of sub-threshold SRAM memory cells.

Abstract translation: 本发明公开了一种用于提高亚阈值SRAM存储单元的处理鲁棒性的电路，其用作子阈值SRAM存储单元的辅助电路。 电路的输出连接到子阈值SRAM存储单元的PMOS管和电路中的PMOS管的衬底。 该电路包括用于PMOS管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS管和NMOS管的阈值电压波动，以自适应方式改变子阈值SRAM存储单元中的PMOS管的衬底电压和电路中的PMOS管的衬底电压 从而调节PMOS管的阈值电压，使得PMOS管的阈值电压与NMOS管的阈值电压相匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限，有效提高了亚阈值SRAM存储单元的工艺稳健性。

公开(公告)号：US20150008971A1

公开(公告)日：2015-01-08

申请号：US14369652

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: H03K3/013 ,  H03K3/012

CPC classification number: H03K3/013 ,  G11C11/417 ,  G11C11/419 ,  H03K3/012

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。

公开(公告)号：US09236115B2

公开(公告)日：2016-01-12

申请号：US14369651

申请日：2012-12-27

Applicant: SOUTHEAST UNIVERSITY

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: G11C11/419 ,  G11C11/417 ,  H01L27/11 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/417 ,  H01L27/1104

Abstract: A circuit for improving process robustness of sub-threshold SRAM memory cells serves as an auxiliary circuit for a sub-threshold SRAM memory cell. The output of the circuit is connected to PMOS transistors of the sub-threshold SRAM memory cell and substrate of PMOS transistors in the circuit. The circuit includes a detection circuit for threshold voltages of the PMOS transistors and a differential input and single-ended output amplifier. The circuit changes the substrate voltage of the PMOS transistors in the sub-threshold SRAM memory cell and the PMOS transistors in the circuit in a self-adapting manner by detecting threshold voltage fluctuations of PMOS and NMOS transistor resulted from process fluctuations and thereby regulates the threshold voltages of the PMOS transistors, so that the threshold voltages of the PMOS and NMOS transistors match. The circuit improves the noise margin of sub-threshold SRAM memory cells and the process robustness of sub-threshold SRAM memory cells.

Abstract translation: 用于提高子阈值SRAM存储单元的工艺稳健性的电路用作子阈值SRAM存储单元的辅助电路。 电路的输出端连接到子阈值SRAM存储单元的PMOS晶体管和电路中PMOS晶体管的衬底。 该电路包括用于PMOS晶体管的阈值电压的检测电路和差分输入和单端输出放大器。 该电路通过检测来自过程波动的PMOS和NMOS晶体管的阈值电压波动，以自适应的方式改变子阈值SRAM存储单元中的PMOS晶体管的衬底电压和电路中的PMOS晶体管，从而调节阈值 PMOS晶体管的电压，使得PMOS和NMOS晶体管的阈值电压匹配。 该电路提高了亚阈值SRAM存储单元的噪声容限和子阈值SRAM存储单元的工艺稳健性。

公开(公告)号：US08922265B1

公开(公告)日：2014-12-30

申请号：US14369652

申请日：2012-12-27

Applicant: Southeast University

Inventor： Na Bai ,  Longxing Shi ,  Jun Yang ,  Xinning Liu ,  Jiafeng Zhu ,  Yue Feng ,  Cai Gong ,  Fei Pan ,  Hong Chang ,  Yifeng Deng ,  Yuan Chen ,  Yingcheng Xia

IPC: H03L5/00 ,  H03K3/013 ,  H03K3/012

CPC classification number: H03K3/013 ,  G11C11/417 ,  G11C11/419 ,  H03K3/012

Abstract: Disclosed is a noise current compensation circuit. The circuit is provided with two input and output terminals A and B, and two control terminals CON and CONF. The control terminals control a work mode (work state and pre-charge state) of the compensation circuit. The compensation circuit consists of 7 PMOS transistors and 8 NMOS transistors. In the normal work state, by detecting changes of potential change rate of two signal lines in an original circuit, the noise current compensation circuit automatically enables one end of the original circuit that discharges slowly to discharge a signal more slowly, and enables one end of the original circuit that discharges rapidly to discharge a signal more rapidly, thus eliminating the influence of the noise current on the circuit and providing assistance for correct identification of subsequent circuit signals. The current compensation circuit can be used for an SRAM bit line leakage current compensation circuit, because the existence of a large leakage current on the SRAM bit line leads to the decreasing of a voltage difference between two ends of the bit line, resulting in that a subsequent circuit cannot correctly identify a signal.

Abstract translation: 公开了一种噪声电流补偿电路。 该电路设有两个输入和输出端子A和B，以及两个控制端子CON和CONF。 控制端子控制补偿电路的工作模式（工作状态和预充电状态）。 补偿电路由7个PMOS晶体管和8个NMOS晶体管组成。 在正常工作状态下，通过检测原始电路中两根信号线的电位变化率的变化，噪声电流补偿电路自动使缓慢放电的原电路的一端缓慢放电，使一端 原始电路快速放电以更快地放电信号，从而消除噪声电流对电路的影响，并为后续电路信号的正确识别提供帮助。 电流补偿电路可以用于SRAM位线漏电流补偿电路，因为SRAM位线上存在大的漏电流导致位线两端之间的电压差减小，导致 后续电路无法正确识别信号。