公开(公告)号：US20180189229A1

公开(公告)日：2018-07-05

申请号：US15423272

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe DESOLI ,  Thomas BOESCH ,  Nitin CHAWLA ,  Surinder Pal SINGH ,  Elio GUIDETTI ,  Fabio Giuseppe DE AMBROGGI ,  Tommaso MAJO ,  Paolo Sergio ZAMBOTTI

IPC: G06F15/78 ,  G06N3/04 ,  G06F13/40

Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

公开(公告)号：US20180306656A1

公开(公告)日：2018-10-25

申请号：US15957819

申请日：2018-04-19

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Elio GUIDETTI ,  Mohammad ABBASI GAVARTI ,  Daniele CALTABIANO ,  Gabriele BERTAGNOLI

IPC: G01L1/18 ,  G01L25/00

CPC classification number: G01L1/18 ,  G01L5/162 ,  G01L25/00 ,  G01M5/0041 ,  G01M5/0083

Abstract: A stress sensor formed by a membrane plate; a first bonding region arranged on top of the membrane plate; a cover plate arranged on top of the first bonding region, the first bonding region bonding the membrane plate to the cover plate; three-dimensional piezoresistive elements extending across the membrane plate that are embedded in the bonding layer; and planar piezoresistive elements that extend across the membrane plate and are surrounded by and separated from the bonding layer.

公开(公告)号：US20140019727A1

公开(公告)日：2014-01-16

申请号：US13936886

申请日：2013-07-08

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Beijing) R&D Company Ltd.

Inventor： PengFei ZHU ,  HongXia SUN ,  YongQiang WU ,  Elio GUIDETTI

IPC: G06F9/30

CPC classification number: G06F9/3004 ,  G06F9/30043 ,  G06F9/30112 ,  G06F9/30127 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3893

Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.

Abstract translation: 给出了一种改进的平衡吞吐量数据路径架构的装置和方法，用于有效实现计算机硬件中过滤，卷积和相关的数字信号处理算法，其中数据和系数缓冲器都可以实现为滑动窗口。 该架构使用从地址发生器单元到乘法累加执行单元的多路复用器和数据路径分支。 通过在地址发生器到执行单元的数据通路与寄存器到执行单元的数据通路之间进行选择，可以克服由不对称寻址对系数引起的不平衡吞吐量和乘法累加气泡循环。 改进的平衡吞吐量数据路径架构在实现数字信号处理算法时可以实现每个周期的高乘法累加运算速率。

公开(公告)号：US20130173865A1

公开(公告)日：2013-07-04

申请号：US13692744

申请日：2012-12-03

Applicant: STMicroelectronics (Beijing) R&D Company Ltd. ,  STMicroelectronics, s.r.l.

Inventor： YongQiang WU ,  PengFei ZHU ,  HongXia SUN ,  Elio GUIDETTI

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F9/30098 ,  G06F9/3012 ,  G06F9/30141

Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.

Abstract translation: 注册文件组织用于支持来自多个处理器或管道的多个访问。 该共享寄存器文件针对包含高性能（HP）和低功耗（LP）内核的多处理器设备进行组织。 共享寄存器文件包括单独的HP和LP存储单元，耦合到单独的HP和LP写入和读取端口。