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1.发明申请MODIFIED BALANCED THROUGHPUT DATA-PATH ARCHITECTURE FOR SPECIAL CORRELATION APPLICATIONS 有权用于特殊关联应用的修改平衡数据路径架构公开(公告)号：US20140019727A1
公开(公告)日：2014-01-16
申请号：US13936886
申请日：2013-07-08
Inventor： PengFei ZHU , HongXia SUN , YongQiang WU , Elio GUIDETTI
IPC: G06F9/30
CPC classification number: G06F9/3004 , G06F9/30043 , G06F9/30112 , G06F9/30127 , G06F9/345 , G06F9/3824 , G06F9/3893
Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.
Abstract translation: 给出了一种改进的平衡吞吐量数据路径架构的装置和方法，用于有效实现计算机硬件中过滤，卷积和相关的数字信号处理算法，其中数据和系数缓冲器都可以实现为滑动窗口。 该架构使用从地址发生器单元到乘法累加执行单元的多路复用器和数据路径分支。 通过在地址发生器到执行单元的数据通路与寄存器到执行单元的数据通路之间进行选择，可以克服由不对称寻址对系数引起的不平衡吞吐量和乘法累加气泡循环。 改进的平衡吞吐量数据路径架构在实现数字信号处理算法时可以实现每个周期的高乘法累加运算速率。
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Patent Agency Ranking
2.发明申请REGISTER FILE ORGANIZATION TO SHARE PROCESS CONTEXT FOR HETEROGENEOUS MULTIPLE PROCESSORS OR JOINT PROCESSOR 有权注册文件组织分享异构多处理器或联合处理器的过程公开(公告)号：US20130173865A1
公开(公告)日：2013-07-04
申请号：US13692744
申请日：2012-12-03
Inventor： YongQiang WU , PengFei ZHU , HongXia SUN , Elio GUIDETTI
IPC: G06F12/08
CPC classification number: G06F12/0802 , G06F9/30098 , G06F9/3012 , G06F9/30141
Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.
Abstract translation: 注册文件组织用于支持来自多个处理器或管道的多个访问。 该共享寄存器文件针对包含高性能（HP）和低功耗（LP）内核的多处理器设备进行组织。 共享寄存器文件包括单独的HP和LP存储单元，耦合到单独的HP和LP写入和读取端口。
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3.发明授权Modified balanced throughput data-path architecture for special correlation applications 有权用于特殊相关应用的改进的平衡吞吐量数据路径架构公开(公告)号：US09424033B2
公开(公告)日：2016-08-23
申请号：US13936886
申请日：2013-07-08
Inventor： PengFei Zhu , HongXia Sun , YongQiang Wu , Elio Guidetti
CPC classification number: G06F9/3004 , G06F9/30043 , G06F9/30112 , G06F9/30127 , G06F9/345 , G06F9/3824 , G06F9/3893
Abstract: Apparatus and method for a modified, balanced throughput data-path architecture is given for efficiently implementing the digital signal processing algorithms of filtering, convolution and correlation in computer hardware, in which both data and coefficient buffers can be implemented as sliding windows. This architecture uses a multiplexer and a data path branch from the Address Generator unit to the multiply-accumulate execution unit. By selecting between the data path of Address Generator to execution unit and the data path of register to execution unit, the unbalanced throughput and multiply-accumulate bubble cycles caused by misaligned addressing on coefficients can be overcome. The modified balanced throughput data-path architecture can achieve a high multiply-accumulate operation rate per cycle in implementing digital signal processing algorithms.
Abstract translation: 给出了一种改进的平衡吞吐量数据路径架构的装置和方法，用于有效实现计算机硬件中过滤，卷积和相关的数字信号处理算法，其中数据和系数缓冲器都可以实现为滑动窗口。 该架构使用从地址发生器单元到乘法累加执行单元的多路复用器和数据路径分支。 通过在地址发生器到执行单元的数据通路与寄存器到执行单元的数据通路之间进行选择，可以克服由不对称寻址对系数引起的不平衡吞吐量和乘法累加气泡循环。 改进的平衡吞吐量数据路径架构在实现数字信号处理算法时可以实现每个周期的高乘法累加运算速率。
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4.发明授权Register file organization to share process context for heterogeneous multiple processors or joint processor 有权注册文件组织以分享异构多处理器或联合处理器的进程上下文公开(公告)号：US09015377B2
公开(公告)日：2015-04-21
申请号：US13692744
申请日：2012-12-03
Inventor： YongQiang Wu , PengFei Zhu , HongXia Sun , Elio Guidetti
CPC classification number: G06F12/0802 , G06F9/30098 , G06F9/3012 , G06F9/30141
Abstract: A register file organization is used to support multiple accesses from more than one processor or pipeline. This shared register file is organized for a multiple processor device that includes a high performance (HP) and a low power (LP) core. The shared register file includes separate HP and LP storage units coupled to separate HP and LP write and read ports.
Abstract translation: 注册文件组织用于支持来自多个处理器或管道的多个访问。 该共享寄存器文件针对包含高性能（HP）和低功耗（LP）内核的多处理器设备进行组织。 共享寄存器文件包括单独的HP和LP存储单元，耦合到单独的HP和LP写入和读取端口。
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5.发明授权Data accessing method to boost performance of FIR operation on balanced throughput data-path architecture 有权数据访问方法，以提高平衡吞吐量数据路径架构上FIR操作的性能公开(公告)号：US09082476B2
公开(公告)日：2015-07-14
申请号：US13936849
申请日：2013-07-08
Inventor： PengFei Zhu , HongXia Sun , YongQiang Wu , Elio Guidetti
CPC classification number: G11C19/00 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/3012 , G06F9/3887 , G06F9/3891 , G06F9/3893
Abstract: An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.
Abstract translation: 公开了一种通过使用修改的平衡数据结构和访问架构来实现涉及乘法累加（MAC）操作的数字信号处理操作的装置和方法。 该架构维护连接一个地址生成单元，一个寄存器文件和一个MAC执行单元的数据路径。 寄存器文件具有各个寄存器的分层分组组织，可以减少由于存储器未对准而导致的气泡循环。 该架构使用并行执行，并且可以在每个周期中实现两个或更多个MAC操作。
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6.发明申请NOVEL DATA ACCESSING METHOD TO BOOST PERFORMANCE OF FIR OPERATION ON BALANCED THROUGHPUT DATA-PATH ARCHITECTURE 有权新型数据访问方法，以提高平衡运行对平衡数据路径结构的性能公开(公告)号：US20140019679A1
公开(公告)日：2014-01-16
申请号：US13936849
申请日：2013-07-08
Inventor： PengFei Zhu , HongXia Sun , YongQiang Wu , Elio Guidetti
IPC: G11C19/00
CPC classification number: G11C19/00 , G06F9/3001 , G06F9/30036 , G06F9/3004 , G06F9/3012 , G06F9/3887 , G06F9/3891 , G06F9/3893
Abstract: An apparatus and method are disclosed to implement digital signal processing operations involving multiply-accumulate (MAC) operations, by using a modified balanced data structure and accessing architecture. This architecture maintains a data-path connecting one address generation unit, one register file and one MAC execution unit. The register file has a hierarchical grouping organization of individual registers, which reduces bubble cycles caused by memory misalignments. This architecture uses parallel execution and can achieve two or more MAC operations per cycle.
Abstract translation: 公开了一种通过使用修改的平衡数据结构和访问架构来实现涉及乘法累加（MAC）操作的数字信号处理操作的装置和方法。 该架构维护连接一个地址生成单元，一个寄存器文件和一个MAC执行单元的数据路径。 寄存器文件具有各个寄存器的分层分组组织，可以减少由于存储器未对准而导致的气泡循环。 该架构使用并行执行，并且可以在每个周期中实现两个或更多个MAC操作。
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