公开(公告)号：US12118451B2

公开(公告)日：2024-10-15

申请号：US15423272

申请日：2017-02-02

Applicant: STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Giuseppe Desoli ,  Thomas Boesch ,  Nitin Chawla ,  Surinder Pal Singh ,  Elio Guidetti ,  Fabio Giuseppe De Ambroggi ,  Tommaso Majo ,  Paolo Sergio Zambotti

IPC: G06N3/04 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

CPC classification number: G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

Abstract: Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.