公开(公告)号：US12112113B2

公开(公告)日：2024-10-08

申请号：US17194003

申请日：2021-03-05

申请人： Apple Inc.

发明人： Sergio Kolor ,  Dany Davidov ,  Nir Leshem ,  Mark Pilip ,  Lior Zimet

IPC分类号： G06F30/392 ,  G06F13/40 ,  G06F115/02

CPC分类号： G06F30/392 ,  G06F13/4068 ,  G06F2115/02

摘要： A system includes a first instance and a second instance of an integrated circuit. The integrated circuits include respective external interfaces with a physical pin layout having transmit and receive pins for a particular bus located in complementary positions relative to an axis of symmetry. The external interfaces of the first and second instances of the integrated circuit are positioned such that the transmit and receive pins for the given I/O signal on the first instance are aligned, respectively, with the receive and transmit pins for the given I/O signal on the second instance.

公开(公告)号：US12093631B2

公开(公告)日：2024-09-17

申请号：US17500768

申请日：2021-10-13

申请人： Black Sesame Technologies Inc.

发明人： Junwei Yang ,  Wei Cai ,  Maosheng Xue

IPC分类号： G06F30/398 ,  G06F111/20 ,  G06F115/02

CPC分类号： G06F30/398 ,  G06F2111/20 ,  G06F2115/02

摘要： A method for system-on-chip (SoC) verification is disclosed. The method includes: establishing a component library including at least an interface protocol component, a bus protocol component and a verification component for the SoC; creating a control file according to a verification requirement; establishing a software library for each processor of the SoC to run according to the verification requirement, and establishing an excitation library for corresponding components in the component library; establishing a script library including multiple script files based on the verification requirement and the control file; parsing, by the script, the control file of the verification platform to obtain control parameters of the verification platform when a verification scenario is determined; selecting a required component from the component library and selecting a required excitation from the excitation library to generate the verification platform according to the control parameters; and verifying the SoC by the verification platform.

公开(公告)号：US11657203B2

公开(公告)日：2023-05-23

申请号：US17116344

申请日：2020-12-09

申请人： ARTERIS, INC.

发明人： Moez Cherif ,  Benoit de Lescure

IPC分类号： G06F30/392 ,  G06F15/78 ,  G06F115/02 ,  G06F111/20 ,  G06F111/04

CPC分类号： G06F30/392 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2111/04 ,  G06F2111/20 ,  G06F2115/02

摘要： A process is disclosed that automatically creates a network-on-chip (NoC) very quickly using a set of constraints, which are requirements for the NoC. The process takes a set of constraints as inputs and produces a NoC with all its elements configured and a placement of such elements on the floorplan of the chip.

公开(公告)号：US12112115B2

公开(公告)日：2024-10-08

申请号：US18328800

申请日：2023-06-05

申请人： ZHEJIANG LAB

发明人： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC分类号： G06F30/396 ,  G06F115/02 ,  G06F119/22 ,  H01L27/02

CPC分类号： G06F30/396 ,  H01L27/0207 ,  G06F2115/02 ,  G06F2119/22

摘要： A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

公开(公告)号：US20240220692A1

公开(公告)日：2024-07-04

申请号：US18530164

申请日：2023-12-05

申请人： ARTERIS, INC.

发明人： Benoit de LESCURE ,  Moez CHERIF

IPC分类号： G06F30/327 ,  G06F115/02 ,  G06F115/08

CPC分类号： G06F30/327 ,  G06F2115/02 ,  G06F2115/08

摘要： A tool for executing performance-aware topology synthesis of a network, such as a network-on-chip (NoC). The tool is provided with network information. The tool uses the network information to automatically stabilizes data width and clock speed for each element in the network that meet the network's constraints and performance requirements. The tool is able to provide the performance-aware topology synthesis rapidly, while honoring the objectives and the network's constraints.

公开(公告)号：US20230385500A1

公开(公告)日：2023-11-30

申请号：US18031794

申请日：2021-08-31

申请人： Siemens Aktiengesellschaft

发明人： Bernhard FISCHER ,  Martin MATSCHNIG ,  Joubin DJAVAN ,  Christian CECH ,  Thomas HINTERSTOISSER

IPC分类号： G06F30/343 ,  G06F21/57

CPC分类号： G06F30/343 ,  G06F21/572 ,  G06F2115/02

摘要： A method for checking the integrity of functional units that are reloadable during runtime of an electronic component in a dynamically reconfigurable region of the electronic component, wherein the electronic component, which is formed as a programmable logic circuit, has, in addition to a static region, a dynamically reconfigurable region and the reloadable functional units have predefined interfaces, where an associated twin functional unit is configured in a specified subregion of the dynamically reconfigurable region for each reloadable functional unit, a reloadable functional unit is loaded into a specified subregion of the dynamically reconfigurable region, supplied with identical input data to the associated twin functional unit, and executed in parallel with the twin functional unit, and where output data of the reloaded functional unit and associated twin functional unit are compared and the reloaded functional unit is enabled if a match between the two output data is found.

公开(公告)号：US12118451B2

公开(公告)日：2024-10-15

申请号：US15423272

申请日：2017-02-02

申请人： STMICROELECTRONICS S.R.L. ,  STMICROELECTRONICS INTERNATIONAL N.V.

发明人： Giuseppe Desoli ,  Thomas Boesch ,  Nitin Chawla ,  Surinder Pal Singh ,  Elio Guidetti ,  Fabio Giuseppe De Ambroggi ,  Tommaso Majo ,  Paolo Sergio Zambotti

IPC分类号： G06N3/04 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/0464 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/445 ,  G06F13/40 ,  G06F15/78 ,  G06F115/02 ,  G06F115/08 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

CPC分类号： G06N3/0464 ,  G06F30/327 ,  G06F30/34 ,  G06F30/347 ,  G06N3/044 ,  G06N3/045 ,  G06N3/047 ,  G06N3/084 ,  G06N20/00 ,  G06N20/10 ,  G06F9/44505 ,  G06F13/4022 ,  G06F15/7817 ,  G06F2115/02 ,  G06F2115/08 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06N7/01

摘要： Embodiments are directed towards a system on chip (SoC) that implements a deep convolutional network heterogeneous architecture. The SoC includes a system bus, a plurality of addressable memory arrays coupled to the system bus, at least one applications processor core coupled to the system bus, and a configurable accelerator framework coupled to the system bus. The configurable accelerator framework is an image and deep convolutional neural network (DCNN) co-processing system. The SoC also includes a plurality of digital signal processors (DSPs) coupled to the system bus, wherein the plurality of DSPs coordinate functionality with the configurable accelerator framework to execute the DCNN.

公开(公告)号：US20230401367A1

公开(公告)日：2023-12-14

申请号：US18238562

申请日：2023-08-28

申请人： FUZHOU UNIVERSITY

发明人： Wenzhong GUO ,  Huayang CAI ,  Genggeng LIU ,  Xing HUANG ,  Guolong CHEN

IPC分类号： G06F30/337 ,  G06F17/11

CPC分类号： G06F30/337 ,  G06F17/11 ,  G06F2115/02

摘要： A DRL-based control logic design method for continuous microfluidic biochips is provided. Firstly, an integer linear programming model is for effectively solving multi-channel switching calculation to minimize the number of time slices required by the control logic. Secondly, a control logic synthesis method based on deep reinforcement learning, which uses a double deep Q network and two Boolean logic simplification techniques to find a more effective pattern allocation scheme for the control logic.

公开(公告)号：US20230394210A1

公开(公告)日：2023-12-07

申请号：US17833439

申请日：2022-06-06

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Nuo Xu ,  Zhengping Jiang ,  Zhiqiang Wu

IPC分类号： G06F30/331 ,  G06F30/337

CPC分类号： G06F30/331 ,  G06F30/337 ,  G06F2115/02

摘要： An exemplary method for semiconductor device simulation includes receiving a device structure, generating a mesh for the device structure, simulating electrical behavior of the device structure using the mesh, and adaptively adjusting the mesh during the simulating. The adaptively adjusting the mesh includes performing a multi-level restriction-prolongation (MLRP) process that decreases and increases a resolution of the mesh. The semiconductor device simulation can be performed by a semiconductor simulation system that includes a central processing unit, a memory, and a hardware accelerator. The MLRP process is at least partially parallelized on the hardware accelerator, such as a GPU.

公开(公告)号：US11748536B2

公开(公告)日：2023-09-05

申请号：US17297745

申请日：2019-11-27

申请人： SiFive, Inc.

发明人： Yunsup Lee ,  Michael Cave

IPC分类号： G06F30/327 ,  G06F30/33 ,  G06F115/02 ,  G06F115/12

CPC分类号： G06F30/327 ,  G06F30/33 ,  G06F2115/02 ,  G06F2115/12

摘要： Systems and methods are disclosed for automated generation of integrated circuit designs and associated data. These allow the design of processors and SoCs by a single, non-expert who understands high-level requirements; allow the en masse exploration of the design-space through the generation processors across the design-space via simulation, or emulation; allow the easy integration of IP cores from multiple third parties into an SoC; allow for delivery of a multi-tenant service for producing processors and SoCs that are customized while also being pre-verified and delivered with a complete set of developer tools, documentation and related outputs. Some embodiments, provide direct delivery, or delivery into a cloud hosting environment, of finished integrated circuits embodying the processors and SoCs.