公开(公告)号：US20020080658A1

公开(公告)日：2002-06-27

申请号：US09996082

申请日：2001-11-28

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Tiziana Signorelli ,  Francesco Pulvirenti ,  Calogero Ribellino

IPC: G11C007/00

CPC classification number: G06F11/006 ,  H01L2223/5444

Abstract: A circuit architecture and a method for performing a trimming operation directly on an application board, or after the operation of packaging integrated electronic devices. The circuit architecture includes at least one non-volatile memory unit (3) having non-volatile memory elements (5) and a circuit (17,19) for modifying the state of the memory elements (5), a first multifunctional input pin (8) whereon a sequence (25) of trimming data is received, a second multifunctional input pin (9) whereon a timing signal of the trimming operations is received, and an additional access pin (7) for switching the circuit architecture operation from a normal mode over to a trimming mode. This circuit architecture further includes a volatile memory unit (2) associated with the non-volatile memory unit (3) for storing the non-volatile memory (3) state at power-on or at a simulating phase, and storing the sequence (25) of trimming data at a programming phase; an interface (6) is provided between the first multifunctional input pin (8), the second multifunctional input pin (9), and the additional access pin (7), the at least one non-volatile memory unit (3), and the volatile memory unit (2), for initially storing the sequence of trimming data (25) into the volatile memory unit (2) and subsequently timing the trimming operation.

Abstract translation: 一种用于在应用板上直接执行修整操作或者在封装集成电子设备之后进行修整操作的电路架构和方法。 电路架构包括至少一个具有非易失性存储元件（5）的非易失性存储器单元（3）和用于修改存储元件（5）的状态的电路（17,19），第一多功能输入引脚 8），其中接收到修剪数据的序列（25），其中接收到修剪操作的定时信号的第二多功能输入引脚（9）和用于将电路架构操作从正常切换的附加接入引脚（7） 模式切换到修剪模式。 该电路架构还包括与非易失性存储器单元（3）相关联的易失性存储器单元（2），用于在通电或模拟阶段存储非易失性存储器（3）状态，并存储序列（25 ）在编程阶段修剪数据; 在第一多功能输入引脚（8），第二多功能输入引脚（9）和附加存取引脚（7）之间提供接口（6），所述至少一个非易失性存储单元（3）和 易失性存储器单元（2），用于初始将修整数据（25）的序列存储到易失性存储器单元（2）中，并且随后对修整操作进行定时。