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    Fast and accurate anomaly detection explanations with forward-backward feature importance
    2.
    发明授权
    Fast and accurate anomaly detection explanations with forward-backward feature importance 有权

    公开(公告)号：US11966275B2

    公开(公告)日：2024-04-23

    申请号：US17992743

    申请日：2022-11-22

    Applicant: Oracle International Corporation

    Inventor： Ali Seyfi ,  Yasha Pushak ,  Hesam Fathi Moghadam ,  Sungpack Hong ,  Hassan Chafi

    IPC: G06F11/00 ,  G06N20/00

    CPC classification number: G06F11/006 ,  G06N20/00 ,  G06F2201/82

    Abstract: The present invention relates to machine learning (ML) explainability (MLX). Herein are local explanation techniques for black box ML models based on coalitions of features in a dataset. In an embodiment, a computer receives a request to generate a local explanation of which coalitions of features caused an anomaly detector to detect an anomaly. During unsupervised generation of a new coalition, a first feature is randomly selected from features in a dataset. Which additional features in the dataset can join the coalition, because they have mutual information with the first feature that exceeds a threshold, is detected. For each feature that is not in the coalition, values of the feature are permuted in imperfect copies of original tuples in the dataset. An average anomaly score of the imperfect copies is measured. Based on the average anomaly score of the imperfect copies, a local explanation is generated that references (e.g. defines) the coalition.

    Characterizing Fault Injection on Power Distribution Networks with Voltage Sensors
    5.
    发明公开
    Characterizing Fault Injection on Power Distribution Networks with Voltage Sensors 审中-公开

    公开(公告)号：US20230305612A1

    公开(公告)日：2023-09-28

    申请号：US17706186

    申请日：2022-03-28

    Applicant: MITRE Corporation

    Inventor： Michael J. Paquette ,  Brian D. Marquis

    IPC: G06F1/30 ,  G06F11/00

    CPC classification number: G06F1/30 ,  G06F11/006

    Abstract: Power and electromagnetic fault injection vulnerabilities in an integrated circuit (IC) can be characterized sampling one or more integrated timing sensors in real-time or by equivalent-time sampling. To achieve equivalent-time sampling, a series of fault injection attempts are performed. An array of timing sensors implemented in part of the IC capture a measure of relative propagation delay, which fluctuates proportionally with instantaneous voltage. Increased voltage fluctuation can indicate elevated probability of faults in digital logic. Related apparatus, systems, techniques and articles are also described.

    COMPUTING DEVICE NOTIFICATION MANAGEMENT SOFTWARE
    6.
    发明公开
    COMPUTING DEVICE NOTIFICATION MANAGEMENT SOFTWARE 审中-公开

    公开(公告)号：US20230267026A1

    公开(公告)日：2023-08-24

    申请号：US18309402

    申请日：2023-04-28

    Applicant: Salesforce, Inc.

    Inventor： Abhijit Sur ,  Charles Hart Isaacs

    IPC: G06F11/07 ,  G06F11/00

    CPC classification number: G06F11/0709 ,  G06F11/0772 ,  G06F11/006 ,  G06F11/0793

    Abstract: Techniques disclosed herein relate to managing notifications to a user associated with a computing device. The notifications correspond to a response to an indication of an exception condition on the computing device. The response to the exception condition includes a plurality of steps, including computer-implemented steps in which data objects output a plurality of notifications for the user. These notifications are processed by a notification choreographer and used to prepare a unified status communication. The unified status communication is output to the user and depicts information corresponding to a plurality of the notifications.

    MEMORY ACCESS CONTROL USING ADDRESS ALIASING
    8.
    发明申请
    MEMORY ACCESS CONTROL USING ADDRESS ALIASING 审中-公开

    公开(公告)号：US20190087355A1

    公开(公告)日：2019-03-21

    申请号：US16130858

    申请日：2018-09-13

    Applicant: STMICROELECTRONICS (ROUSSET) SAS

    Inventor： Fabrice ROMAIN

    IPC: G06F12/14 ,  G06F11/00

    CPC classification number: G06F12/1458 ,  G06F11/006 ,  G06F12/1408 ,  G06F2201/805 ,  G06F2212/1052 ,  G06F2221/2141

    Abstract: The present disclosure concerns a memory access control system comprising: a processing device capable of operating in a plurality of operating modes, and of accessing a memory using a plurality of address aliases; and a verification circuit configured: to receive, in relation with a first read operation of a first memory location in the memory, an indication of a first of said plurality of address aliases associated with the first read operation; to verify that a current operating mode of the processing device permits the processing device to access the memory using the first address alias; to receive, during the first read operation, a first marker stored at the first memory location; and to verify, based on the first marker and on the first address alias, that the processing device is permitted to access the first memory location.

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