公开(公告)号：US20230259463A1

公开(公告)日：2023-08-17

申请号：US18109675

申请日：2023-02-14

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics SA

Inventor： Roberta VITTIMANI ,  Federico GOLLER ,  Riccardo ANGRILLI ,  Charles AUBENAS

IPC: G06F12/14

CPC classification number: G06F12/1441 ,  G06F12/1458

Abstract: A processing system includes a communication system and a processing core configured to generate write requests. A circuit has associated a slave interface circuit configured to manage an address sub-range and selectively forward write requests addressed to a given address. Configuration data specifies whether the given address is protected/unprotected and locked/unlocked. In response to a received write request, address and data are extracted and a determination based on the configuration data is made as to whether the extracted address is protected/unprotected, and locked/unlocked. When the extracted address is unprotected or unlocked, the slave interface forwards the write request. When the extracted address is protected and locked, the slave interface generates an unlock signal in response to a comparison of the extracted address with the extracted data, with the unlock signal being asserted when the extracted data satisfy a predetermined rule with respect to the extracted address.

公开(公告)号：US20230280933A1

公开(公告)日：2023-09-07

申请号：US18116372

申请日：2023-03-02

Applicant: STMicroelectronics S.r.l.

Inventor： Federico GOLLER

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0619 ,  G06F3/0673

Abstract: A slave provides second data bits and ECC bits in response to a master read request. First data bits are generated by selecting between the second data bits and third data bits produced from error correcting the second data bits. The third data bits are generated with a delay of one clock cycle with respect to the second data bits. If an address of the read request is stored to a memory, a control signal is set indicating that the first data bits are invalid and this drives selection of the third data bits (with the first data bits now being valid in a following clock cycle). If an error signal is asserted when the address is not stored to the memory, action is taken to store the address to the memory and a further control signal is set to indicate that the read request should be repeated.

公开(公告)号：US20230251795A1

公开(公告)日：2023-08-10

申请号：US17669085

申请日：2022-02-10

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Fabio Enrico Carlo DISEGNI ,  Federico GOLLER ,  Dario FALANGA ,  Michele FEBBRARINO ,  Massimo MONTANARO

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

Abstract: A non-volatile memory receives a data read request from a processing core of a plurality of processing cores. The read request is directed to a data partition of a non-volatile memory. The non-volatile memory determines whether to process the read request using read-while-write collision management. When it is determined to process the read request using read-while-write collision management, an address associated with the read request is stored in an address register of a set of registers associated with the processing core. Write operations directed to the data partition are suspended. A read operation associated with the read request is executed while the write operations are suspended and data responsive to the read operation is stored in one or more data registers of the set of registers. The data stored in the one or more data registers of the set of registers is provided to the processing core.