公开(公告)号：US20020133647A1

公开(公告)日：2002-09-19

申请号：US10005509

申请日：2001-12-04

Applicant: STMicroelectronics, Inc.

Inventor： Christian D. Kasper

IPC: G06F003/00

CPC classification number: G06F13/128 ,  H04L47/10 ,  H04L47/29 ,  H04L47/30 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9078

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract translation: 在FIFO存储器中使用先行水印公开了一种方法和网络设备。 根据本发明，当FIFO存储器中的数据已经越过水印阈值时，从FIFO存储器产生水印中断。 数据脉冲串通过直接存储器存取单元传送到FIFO存储器。 在FIFO存储器处检查先行水印标志，以确定FIFO存储器内是否有足够的存储器空间用于附加数据脉冲串，当先行水印标志指示时，通过直接存储器访问单元传送到FIFO存储器 有足够的内存空间可用。

公开(公告)号：US20040174813A1

公开(公告)日：2004-09-09

申请号：US10785372

申请日：2004-02-24

Applicant: STMicroelectronics, Inc.

Inventor： Christian D. Kasper ,  Elmer H. Guritz

IPC: G06F003/00

CPC classification number: H04L47/30 ,  H04L47/10 ,  H04L47/12 ,  H04L49/90 ,  H04L49/9068 ,  H04L49/9078

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract translation: 公开了一种用于控制以帧排列并最小化拥塞的网络数据流的方法，装置和网络装置，例如在HDLC控制器的接收端口中。 在接收FIFO存储器内产生指示接收FIFO存储器内的帧溢出的状态错误指示符。 响应于状态错误指示器，向主处理器产生指示在接收FIFO存储器内发生帧溢出的早期拥塞中断。 通过增加直接存储器访问（DMA）单元突发大小的字数或修改其他活动进程的时间片之一，丢弃输入帧并接收帧的服务增强。

公开(公告)号：US20040153588A1

公开(公告)日：2004-08-05

申请号：US10758379

申请日：2004-01-15

Applicant: STMicroelectronics, Inc.

Inventor： Christian D. Kasper

IPC: G06F003/00

CPC classification number: H04L49/254 ,  G06F13/28 ,  H04L49/103 ,  H04L49/90 ,  H04L49/901

Abstract: A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.