公开(公告)号：US20030001589A1

公开(公告)日：2003-01-02

申请号：US10135880

申请日：2002-04-29

Applicant: STMicroelectronics, Inc.

Inventor： Tsiu Chiu Chan ,  Elmer H. Guritz ,  Michael J. Callahan JR.

IPC: G01R031/02

CPC classification number: G11C17/18

Abstract: A fuse-redundancy circuit for use in an integrated circuit and method for operating the same. The fuse-redundancy circuit comprises at least two fuses, at least two fuse-control devices, and a status-checking circuit. Each one of the at least two fuse-control devices is operable to control an electric current flowing through a corresponding one of the at least two fuses. The status-checking circuit operable to generate a status signal having (i) a first state when at least one of the at least two fuses is blown, and (ii) a second state otherwise.

Abstract translation: 一种用于集成电路的熔丝冗余电路及其操作方法。 熔丝冗余电路包括至少两个保险丝，至少两个保险丝控制装置和状态检查电路。 所述至少两个熔丝控制装置中的每一个可操作以控制流过所述至少两个保险丝中相应一个的电流。 所述状态检查电路可操作以产生状态信号，所述状态信号具有（i）当所述至少两个保险丝中的至少一个熔丝被熔断时的第一状态，以及（ii）否则为第二状态。

公开(公告)号：US20040174813A1

公开(公告)日：2004-09-09

申请号：US10785372

申请日：2004-02-24

Applicant: STMicroelectronics, Inc.

Inventor： Christian D. Kasper ,  Elmer H. Guritz

IPC: G06F003/00

CPC classification number: H04L47/30 ,  H04L47/10 ,  H04L47/12 ,  H04L49/90 ,  H04L49/9068 ,  H04L49/9078

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract translation: 公开了一种用于控制以帧排列并最小化拥塞的网络数据流的方法，装置和网络装置，例如在HDLC控制器的接收端口中。 在接收FIFO存储器内产生指示接收FIFO存储器内的帧溢出的状态错误指示符。 响应于状态错误指示器，向主处理器产生指示在接收FIFO存储器内发生帧溢出的早期拥塞中断。 通过增加直接存储器访问（DMA）单元突发大小的字数或修改其他活动进程的时间片之一，丢弃输入帧并接收帧的服务增强。