公开(公告)号：US20030123454A1

公开(公告)日：2003-07-03

申请号：US10290766

申请日：2002-11-08

Applicant: STMICROELECTRONICS, INC.

Inventor： Faraydon O. Karim ,  Ramesh Chandra ,  Bernd H. Stramm

IPC: H04L012/28

CPC classification number: H04L49/9031 ,  H04L49/90 ,  H04L49/901

Abstract: A circular buffer storing packets for processing by one or more network processors employs an empty buffer address register identifying where a next received packet should be stored, a next packet address register identifying the next packet to be processed, and a packet-processing address register within each network processor identifying the packet being processed by that network processor. The n-bit addresses to the buffer are mapped or masked from/to the m-bit packet-processing address registers by software, allowing the buffer size to be fully scalable. A dedicated packet retrieval instruction supported by the network processor(s) retrieves a new packet for processing using the next packet address register and copies that into the associated packet-processing address register for use in subsequent accesses. Buffer management is thus independent of the network processor architecture.

Abstract translation: 存储用于由一个或多个网络处理器处理的分组的循环缓冲器使用空缓冲器地址寄存器来标识下一个接收到的分组应该被存储在哪里，下一个分组地址寄存器标识下一个待处理分组，以及一个分组处理地址寄存器 每个网络处理器识别由该网络处理器正在处理的分组。 缓冲区的n位地址通过软件从/到m位数据包处理地址寄存器映射或屏蔽，从而允许缓冲区大小完全可扩展。 由网络处理器支持的专用分组检索指令使用下一个分组地址寄存器检索新的分组进行处理，并将其复制到相关的分组处理地址寄存器中以用于随后的访问。 因此，缓冲区管理与网络处理器架构无关。

公开(公告)号：US20020095450A1

公开(公告)日：2002-07-18

申请号：US09727135

申请日：2000-11-30

Applicant: STMicroelectronics, Inc

Inventor： Faraydon O. Karim ,  Alain Mellan

IPC: G06F007/00

CPC classification number: G06F7/607

Abstract: A method and a bit counting device (100) count bits set to one in a data word of arbitrary size. The bit counting device (100) includes a first data register (110) for storing a data word, an offset register (112) for storing an offset value, a second data register (120), and a one-cycle shifter (114), electrically connected to the first data register (110), to the second data register (120), and to the offset register (112), for shifting the data word by a value stored in the offset register (112) and storing the shifted data word in the second data register (120). The device 100 also includes a third data register (124) and at least one carry save adder (CSA) device (122) organized in a tree structure, and electrically connected to the second data register (120) and to the third data register (124), for counting the number of bits set to one in the data word stored in the second data register (120) and storing in the third data register (124) a value representing the count of bits set to one in the data word.

Abstract translation: 方法和位计数装置（100）将任意大小的数据字中的一个设置为1的计数位。 位计数装置（100）包括用于存储数据字的第一数据寄存器（110），用于存储偏移值的偏移寄存器（112），第二数据寄存器（120）和单周期移位器（114） ，电连接到第一数据寄存器（110）到第二数据寄存器（120）和偏移寄存器（112），用于将数据字移位存储在偏移寄存器（112）中的值，并存储转移的 数据字在第二数据寄存器（120）中。 设备100还包括以树结构组织的第三数据寄存器（124）和至少一个进位存储加法器（CSA）设备（122），并且电连接到第二数据寄存器（120）和第三数据寄存器 124），用于对存储在第二数据寄存器（120）中的数据字中设置为1的比特数进行计数，并在第三数据寄存器（124）中存储表示在数据字中设置为1的比特数的值。

公开(公告)号：US20040088519A1

公开(公告)日：2004-05-06

申请号：US10283653

申请日：2002-10-30

Applicant: STMicroelectronics, Inc.

Inventor： Faraydon O. Karim

IPC: G06F015/00 ,  G06F015/76

CPC classification number: G06F9/4843 ,  G06F9/30098 ,  G06F9/3851

Abstract: A hyperprocessor includes a control processor controlling tasks executed by a plurality of processor cores, each of which may include multiple execution units, or special hardware units. The control processor schedules tasks according to control threads for the tasks created during compilation and comprising a hardware context including register files, a program counter and status bits for the respective task. The tasks are dispatched to the processor cores or special hardware units for parallel, sequential, out-of-order or speculative execution. A universal register file contains data to be operated on by the task, and an interconnect couples at least the processor cores or special hardware units to each other and to the universal register file, allowing each node to communicate with any other node.

Abstract translation: 超处理器包括控制处理器，其控制由多个处理器核执行的任务，每个处理器核可以包括多个执行单元或特殊硬件单元。 控制处理器根据编译期间创建的任务的控制线程调度任务，并且包括包括寄存器文件的硬件上下文，程序计数器和相应任务的状态位。 将任务分派到处理器内核或特殊硬件单元进行并行，顺序，无序或推测执行。 通用寄存器文件包含要由任务操作的数据，并且互连至少将处理器核心或特殊硬件单元彼此耦合到通用寄存器文件，从而允许每个节点与任何其他节点通信。

公开(公告)号：US20020176402A1

公开(公告)日：2002-11-28

申请号：US10090899

申请日：2002-03-05

Applicant: STMICROELECTRONICS, INC.

Inventor： Faraydon O. Karim

IPC: H04L012/66

CPC classification number: H04L49/15 ,  H04L49/109 ,  H04L49/352 ,  H04L49/357

Abstract: An octagonal interconnection network for routing data packets. The interconnection network comprises: 1) eight switching circuits for transferring data packets with each other; 2) eight sequential data links bidirectionally coupling the eight switching circuits in sequence to thereby form an octagonal ring configuration; and 3) four crossing data links, wherein a first crossing data link bidirectionally couples a first switching circuit to a fifth switching circuit, a second crossing data link bidirectionally couples a second switching circuit to a sixth switching circuit, a third crossing data link bidirectionally couples a third switching circuit to a seventh switching circuit, and a fourth crossing data link bidirectionally couples a fourth switching circuit to an eighth switching circuit.

Abstract translation: 用于路由数据包的八角互连网络。 互连网络包括：1）用于彼此传输数据分组的8个切换电路; 2）八个顺序数据链路按顺序耦合八个开关电路从而形成八角形环配置; 以及3）四个交叉数据链路，其中第一交叉数据链路将第一开关电路双向耦合到第五开关电路，第二交叉数据链路将第二开关电路双向耦合到第六开关电路，第三交叉数据链路双向耦合 第七开关电路，第七开关电路和第四交叉数据链路将第四开关电路双向耦合到第八开关电路。

公开(公告)号：US20020095642A1

公开(公告)日：2002-07-18

申请号：US09726927

申请日：2000-11-30

Applicant: STMicroelectronics, Inc.

Inventor： Faraydon O. Karim ,  Kartik V. Talsania ,  Vincent E. Wass

IPC: H03M013/00 ,  G06F011/00

CPC classification number: H03M13/096

Abstract: A method and a computing system compute an incremental checksum corresponding to a data packet. The incremental checksum is computed within one processor cycle of a processor. A first register (102) stores first checksum information corresponding to a data packet. A second register (104) stores second checksum information corresponding to old information being deleted from the data packet. A third register (106) stores third checksum information corresponding to new information being added to the data packet. An incremental checksum circuit (100), electrically connected to the first register (102), to the second register (104), and to the third register (106), provides resulting checksum information corresponding to the data packet after deleting the old information from the data packet and adding the new information to the data packet. The resulting checksum information is selectively stored in the first register (102).

Abstract translation: 方法和计算系统计算对应于数据分组的增量校验和。 在处理器的一个处理器周期内计算增量校验和。 第一寄存器（102）存储对应于数据包的第一校验和信息。 第二寄存器（104）存储对应于从数据分组中删除的旧信息的第二校验和信息。 第三寄存器（106）存储对应于添加到数据分组的新信息的第三校验和信息。 与第一寄存器（102）电连接到第二寄存器（104）和第三寄存器（106）的增量校验和电路（100）在从旧数据包中删除旧信息之后提供对应于数据包的结果校验和信息 数据包，并将新信息添加到数据包中。 产生的校验和信息被选择性地存储在第一寄存器（102）中。