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公开(公告)号：US09755051B2
公开(公告)日：2017-09-05
申请号：US14969911
申请日：2015-12-15
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/66 , H01L29/165 , H01L21/8238 , H01L27/092 , H01L21/265 , H01L29/78 , H01L29/10
CPC classification number: H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66628 , H01L29/66651 , H01L29/7834
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
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公开(公告)号：US09000564B2
公开(公告)日：2015-04-07
申请号：US13725837
申请日：2012-12-21
Applicant: STMicroelectronics, Inc. , International Business Machines Corporation , GlobalFoundries Inc. , Samsung Electronics Co., Ltd.
Inventor： Pietro Montanini , Gerald Leake, Jr. , Brett H. Engel , Roderick Mason Miller , Ju Youn Kim
CPC classification number: H01L28/20 , H01L27/0629 , H01L27/0802 , H01L29/66545
Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.
Abstract translation: 使用替代金属栅极（RMG）工艺提供了在金属栅极晶体管旁边创建精密多晶硅电阻的机会。 在牺牲多晶硅栅极的形成期间，也可以由相同的多晶硅膜形成精密多晶硅电阻器。 多晶硅电阻器可以稍微凹进，使得在随后用金属栅极替换牺牲栅极时，保护绝缘层可以覆盖电阻器。 使用这种工艺制造的精密多晶硅电阻器的最终结构比为具有金属栅极晶体管的集成电路提供金属电阻器的现有结构更紧凑和更不复杂。 此外，通过用掺杂剂注入多晶硅膜，调节多晶硅膜厚度或两者，可以将精密多晶硅电阻器自由地调谐为具有所需的薄层电阻。
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公开(公告)号：US20140353741A1
公开(公告)日：2014-12-04
申请号：US13907690
申请日：2013-05-31
Applicant: STMicroelectronics, Inc. , GLOBALFOUNDRIES Inc. , International Business Machines Corporation
Inventor： Pietro Montanini , Raymond Joy , Marta Mottura , Henry K. Utomo
CPC classification number: H01L29/66636 , H01L21/28123 , H01L21/76232 , H01L29/165 , H01L29/7848
Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.
Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。
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公开(公告)号：US09245955B2
公开(公告)日：2016-01-26
申请号：US13931509
申请日：2013-06-28
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/165 , H01L21/8238 , H01L27/092 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/265
CPC classification number: H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66628 , H01L29/66651 , H01L29/7834
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力和对PMOS晶体管的沟道区域的压缩应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。
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公开(公告)号：US20150001583A1
公开(公告)日：2015-01-01
申请号：US13931509
申请日：2013-06-28
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/165 , H01L21/8238 , H01L27/092
CPC classification number: H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66628 , H01L29/66651 , H01L29/7834
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress to the channel region of the NMOS transistors and compressive stress to the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力和对PMOS晶体管的沟道区域的压缩应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。
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Patent Agency Ranking
公开(公告)号：US20140175609A1
公开(公告)日：2014-06-26
申请号：US13725837
申请日：2012-12-21
Applicant: STMicroelectronics, Inc. , Samsung Electronics Co., Ltd. , GlobalFoundries Inc. , International Business Machines Corporation
Inventor： Pietro Montanini , Gerald Leake, JR. , Brett H. Engel , Roderick Mason Miller , Ju Youn Kim
IPC: H01L49/02
CPC classification number: H01L28/20 , H01L27/0629 , H01L27/0802 , H01L29/66545
Abstract: Use of a replacement metal gate (RMG) process provides an opportunity to create precision polysilicon resistors alongside metal gate transistors. During formation of a sacrificial polysilicon gate, the precision polysilicon resistor can also be formed from the same polysilicon film. The polysilicon resistor can be slightly recessed so that a protective insulating layer can cover the resistor during subsequent replacement of the sacrificial gate with a metal gate. The final structure of the precision polysilicon resistor fabricated using such a process is more compact and less complex than existing structures that provide metal resistors for integrated circuits having metal gate transistors. Furthermore, the precision polysilicon resistor can be freely tuned to have a desired sheet resistance by either implanting the polysilicon film with dopants, adjusting the polysilicon film thickness, or both.
Abstract translation: 使用替代金属栅极（RMG）工艺提供了在金属栅极晶体管旁边创建精密多晶硅电阻的机会。 在牺牲多晶硅栅极的形成期间，也可以由相同的多晶硅膜形成精密多晶硅电阻器。 多晶硅电阻器可以稍微凹进，使得在随后用金属栅极替换牺牲栅极时，保护绝缘层可以覆盖电阻器。 使用这种工艺制造的精密多晶硅电阻器的最终结构比为具有金属栅极晶体管的集成电路提供金属电阻器的现有结构更紧凑和更不复杂。 此外，通过用掺杂剂注入多晶硅膜，调节多晶硅膜厚度或两者，可以将精密多晶硅电阻器自由地调谐为具有所需的薄层电阻。
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公开(公告)号：US10103245B2
公开(公告)日：2018-10-16
申请号：US15664225
申请日：2017-07-31
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/66 , H01L29/78 , H01L21/265 , H01L21/8238 , H01L27/092 , H01L29/10 , H01L29/165
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
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公开(公告)号：US20170352741A1
公开(公告)日：2017-12-07
申请号：US15664225
申请日：2017-07-31
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/66 , H01L29/10 , H01L21/8238 , H01L21/265 , H01L27/092 , H01L29/78 , H01L29/165
CPC classification number: H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66628 , H01L29/66651 , H01L29/7834
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
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公开(公告)号：US20160099339A1
公开(公告)日：2016-04-07
申请号：US14969911
申请日：2015-12-15
Applicant: STMicroelectronics, Inc.
Inventor： John H. Zhang , Pietro Montanini
IPC: H01L29/66 , H01L21/265 , H01L21/8238
CPC classification number: H01L29/66636 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L27/092 , H01L29/1054 , H01L29/165 , H01L29/66568 , H01L29/66628 , H01L29/66651 , H01L29/7834
Abstract: An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.
Abstract translation: 集成电路管芯包括硅衬底。 在硅衬底上形成PMOS和NMOS晶体管。 通过向NMOS晶体管的沟道区域引入拉伸应力并进入PMOS晶体管的沟道区域中的压应力来增加PMOS和NMOS晶体管的载流子迁移率。 通过在NMOS晶体管的沟道区域的下方包含SiGe区域来引入拉伸应力。 通过在PMOS晶体管的源极和漏极区域中包括SiGe的区域来引入压缩应力。
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公开(公告)号：US08987827B2
公开(公告)日：2015-03-24
申请号：US13907690
申请日：2013-05-31
Applicant: STMicroelectronics, Inc. , International Business Machines Corporation , GLOBALFOUNDRIES Inc.
Inventor： Pietro Montanini , Raymond Joy , Marta Mottura , Henry K. Utomo
CPC classification number: H01L29/66636 , H01L21/28123 , H01L21/76232 , H01L29/165 , H01L29/7848
Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.
Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。
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