公开(公告)号：US11322363B2

公开(公告)日：2022-05-03

申请号：US16892732

申请日：2020-06-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Julien Borrel ,  Magali Gregoire

IPC: H01L21/3205 ,  H01L21/321 ,  H01L21/265 ,  H01L21/324 ,  H01L21/762 ,  H01L29/45

Abstract: Atoms are implanted in a semiconductor region at a higher concentration in a peripheral part of the semiconductor region than in a central part of the semiconductor region. A metallic region is then formed to cover the semiconductor region. A heat treatment is the performed to form an intermetallic region from the metallic region and the semiconductor region.

公开(公告)号：US11038017B2

公开(公告)日：2021-06-15

申请号：US16279361

申请日：2019-02-19

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Julien Borrel

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732 ,  H01L21/265

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.

公开(公告)号：US09911827B2

公开(公告)日：2018-03-06

申请号：US15372930

申请日：2016-12-08

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Louis Hutin ,  Julien Borrel ,  Yves Morand ,  Fabrice Nemouchi

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L29/66643 ,  H01L29/0895 ,  H01L29/66636 ,  H01L29/7839

Abstract: A process for manufacturing a Schottky barrier field-effect transistor is provided. The process includes: providing a structure including a control gate and a semiconductive layer positioned under the gate and having protrusions that protrude laterally with respect to the gate; anisotropically etching at least one of the protrusions by using the control gate as a mask, so as to form a recess in this protrusion, this recess defining a lateral face of the semiconductive layer; depositing a layer of insulator on the lateral face of the semiconductive layer; and depositing a metal in the recess on the layer of insulator so as to form a contact of metal/insulator/semiconductor type between the deposit of metal and the lateral face of the semiconductive layer.

公开(公告)号：US11621324B2

公开(公告)日：2023-04-04

申请号：US17323170

申请日：2021-05-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Julien Borrel

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/167 ,  H01L29/66 ,  H01L29/737 ,  H01L29/732 ,  H01L21/265

Abstract: A bipolar junction transistor includes an extrinsic collector region buried in a semiconductor substrate under an intrinsic collector region. Carbon-containing passivating regions are provided to delimit the intrinsic collector region. An insulating layer on the intrinsic collector region includes an opening within which an extrinsic base region is provided. A semiconductor layer overlies the insulating layer, is in contact with the extrinsic base region, and includes an opening with insulated sidewalls. The collector region of the transistor is provided between the insulated sidewalls.