公开(公告)号：US09412589B2

公开(公告)日：2016-08-09

申请号：US14501639

申请日：2014-09-30

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： David Barge ,  Philippe Garnier ,  Yves Campidelli

IPC: H01L21/8238 ,  H01L27/092 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/02609 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78618

Abstract: An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

Abstract translation: 集成电路包括在SOI衬底的不同区域上的NMOS晶体管和PMOS晶体管。 每个晶体管包括栅极区域，在栅极区域的侧面上的多层横向绝缘区域，同时也在衬底上。 每个多层横向绝缘区域包括远离基板倾斜的倾斜部分。 源区和漏区在衬底上，并通过相应的多层横向绝缘区与栅极区的侧面分离。 源极和漏极区域具有靠在横向绝缘区域的倾斜部分的倾斜部分。

公开(公告)号：US10186605B1

公开(公告)日：2019-01-22

申请号：US15783109

申请日：2017-10-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexis Gauthier ,  Fabien Deprat ,  Yves Campidelli

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/737 ,  H01L27/06 ,  H01L21/8249 ,  H01L29/417

Abstract: A bipolar transistor is supported by a single-crystal silicon substrate including a collector contact region. A cyclical epitaxy process is performed to provide a collector region of a first conductivity type on the collector contact region that is laterally separated from a silicon layer by an air gap. A second epitaxial region forms a base region of a second conductivity type. Deposited semiconductor material forms an emitter region of the first conductivity type. The collector region, base region and emitter region are located within an opening formed in a stack of insulating layers that includes a sacrificial layer. The sacrificial layer is selectively removed to expose a side wall of the base region. Epitaxial growth from the exposed sidewall forms a base contact region.

公开(公告)号：US20130095636A1

公开(公告)日：2013-04-18

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。

公开(公告)号：US08975154B2

公开(公告)日：2015-03-10

申请号：US13653911

申请日：2012-10-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  Zahra Aitfqirali-Guerry ,  Yves Campidelli ,  Denis Pellissier-Tanon

IPC: H01L21/76 ,  H01L21/762

CPC classification number: H01L21/76237

Abstract: A method for producing at least one deep trench isolation in a semiconductor substrate including silicon and having a front side may include forming at least one cavity in the semiconductor substrate from the front side. The method may include conformally depositing dopant atoms on walls of the cavity, and forming, in the vicinity of the walls of the cavity, a silicon region doped with the dopant atoms. The method may further include filling the cavity with a filler material to form the at least one deep trench isolation.

Abstract translation: 在包括硅并且具有前侧的半导体衬底中产生至少一个深沟槽隔离的方法可以包括从前侧形成半导体衬底中的至少一个空腔。 该方法可以包括在腔的壁上共形沉积掺杂剂原子，并且在空腔的壁附近形成掺杂有掺杂剂原子的硅区。 该方法还可以包括用填充材料填充空腔以形成至少一个深沟槽隔离。