公开(公告)号：US12132119B2

公开(公告)日：2024-10-29

申请号：US17489181

申请日：2021-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan Kim ,  Sunguk Jang ,  Sujin Jung ,  Youngdae Cho

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/06 ,  H01L29/161 ,  H01L29/167 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0259 ,  H01L29/0665 ,  H01L29/167 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618

Abstract: A semiconductor device includes an active region extending in a first direction on a substrate, a plurality of channel layers vertically spaced apart from each other on the active region and including a semiconductor material, a gate structure extending in a second direction on the substrate, and a source/drain region disposed on the active region on at least one side of the gate structure. The gate structure intersects the active region and the plurality of channel layers, and surrounds the plurality of channel layers. The source/drain region contacts the plurality of channel layers and includes first impurities. In at least a portion of the plurality of channel layers, a lower region adjacent to the active region includes the first impurities and second impurities at a first concentration, and an upper region includes the first impurities and the second impurities at a second concentration lower than the first concentration.

公开(公告)号：US20240355910A1

公开(公告)日：2024-10-24

申请号：US18760829

申请日：2024-07-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Jing Lee ,  Ming-Hua Yu

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/167 ,  H01L29/36 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7851 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/4966

Abstract: A method includes recessing a semiconductor fin to form a recess, wherein the semiconductor fin protrudes higher than isolation regions on opposite sides of the semiconductor fin, and performing a first epitaxy to grow a first epitaxy layer extending into the recess. The first epitaxy is performed using a first process gas comprising a silicon-containing gas, silane, and a phosphorous-containing gas. The first epitaxy layer has a first phosphorous atomic percentage. The method further includes performing a second epitaxy to grow a second epitaxy layer extending into the recess and over the first epitaxy layer. The second epitaxy is performed using a second process gas comprising the silicon-containing gas, silane, and the phosphorous-containing gas. The second epitaxy layer has a second phosphorous atomic percentage higher than the first phosphorous atomic percentage.

公开(公告)号：US20240332012A1

公开(公告)日：2024-10-03

申请号：US18290757

申请日：2022-08-05

Applicant: JUSUNG ENGINEERING CO., LTD.

Inventor： Chul Joo HWANG

IPC: H01L21/02

CPC classification number: H01L21/02529 ,  H01L21/02376 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02422 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262

Abstract: Provided is a method for manufacturing an SiC substrate. The method for manufacturing the SiC substrate includes preparing a base, forming any one SiC thin film of an n-type SiC thin film or a p-type SiC thin film on the base, and separating the SiC thin film from the base. The forming of the SiC thin film includes injecting a source gas containing silicon (Si) onto the base, performing primary purge of injecting a purge gas after the injection of the source gas is stopped, injecting a reactant gas containing carbon (C) after the stop of the primary purge, and performing secondary purge of injecting the purge gas after the injection of the reactant gas is stopped. Therefore, in accordance with an exemplary embodiment, the SiC thin film may be deposited at a low temperature to prepare the SiC substrate. Accordingly, power or time required for rising the temperature of the base to form the SiC thin film may be reduced.

公开(公告)号：US20240258099A1

公开(公告)日：2024-08-01

申请号：US18426127

申请日：2024-01-29

Applicant: Littelfuse Semiconductor (Wuxi) Co., Ltd.

Inventor： Xingchong Gu ,  Jifeng Zhou ,  Lei He

IPC: H01L21/02

CPC classification number: H01L21/02129 ,  H01L21/0226 ,  H01L21/02381 ,  H01L21/02576 ,  H01L21/02579

Abstract: Techniques for plating a wafer with electrical glass during fabrication of semiconductor devices in the wafer. An electrical-conductivity network is formed in the wafer by doping a surface region of an isolation structure of the wafer. The isolation structure laterally isolates the semiconductor devices from one another in the wafer. After forming the electrical-conductivity network in the wafer, a glass deposition of a respective plating is formed atop each of one or more plating regions of the wafer.

公开(公告)号：US12048133B2

公开(公告)日：2024-07-23

申请号：US17746693

申请日：2022-05-17

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Nan Wang

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

Abstract: Semiconductor structures is provided. The semiconductor structure includes a semiconductor substrate having at least one first region, a plurality of second regions and a plurality of third regions; at least one second fin formed on one second region of the plurality of second region; at least one third fin formed on one third region of the plurality of third regions; a first epitaxial layer formed in the at least one first fin; and a second epitaxial layer formed in the at least one second fin and the at least one third fin.

公开(公告)号：US12021142B2

公开(公告)日：2024-06-25

申请号：US17876255

申请日：2022-07-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shahaji B. More ,  Huai-Tei Yang ,  Shih-Chieh Chang ,  Cheng-Han Lee

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/167 ,  H01L29/66803 ,  H01L29/161 ,  H01L29/165

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain epitaxial stacks with a boron doping profile and a germanium concentration that can induce external stress to a fully strained SiGe channel. The method includes forming one or more gate structures over a fin, where the fin includes a fin height, a first sidewall, and a second sidewall opposite to the first sidewall. The method also includes forming a first spacer on the first sidewall of the fin and a second spacer on the second sidewall of the fin; etching the fin to reduce the fin height between the one or more gate structures; and etching the first spacer and the second spacer between the one or more gate structures so that the etched first spacer is shorter than the etched second spacer and the first and second etched spacers are shorter than the etched fin. The method further includes forming an epitaxial stack on the etched fin between the one or more gate structures.

公开(公告)号：US20240203730A1

公开(公告)日：2024-06-20

申请号：US18544019

申请日：2023-12-18

Applicant: ASM IP Holding B.V.

Inventor： Rami Khazaka ,  Patricio Romero ,  Michael Eugene Givens ,  Charles Dezelah

IPC: H01L21/02 ,  C30B25/16 ,  C30B25/20 ,  C30B29/52 ,  C30B31/08 ,  C30B33/12

CPC classification number: H01L21/02532 ,  C30B25/16 ,  C30B25/20 ,  C30B29/52 ,  C30B31/08 ,  C30B33/12 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02609 ,  H01L21/02636

Abstract: A method of forming a Si-comprising epitaxial layer selectively on a substrate and a semiconductor processing apparatus is disclosed. Embodiments of the presently described method of forming the Si-comprising epitaxial layer comprise performing a deposition process for forming the Si-comprising epitaxial layer selectively on a first exposed single crystalline surface relative to a second exposed single crystalline surface being different than the first exposed single crystalline surface.

公开(公告)号：US11973143B2

公开(公告)日：2024-04-30

申请号：US16368088

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Benjamin Chu-Kung ,  Subrina Rafique ,  Devin Merrill ,  Ashish Agrawal ,  Harold Kennel ,  Yang Cao ,  Dipanjan Basu ,  Jessica Torres ,  Anand Murthy

IPC: H01L21/84 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7848 ,  H01L21/02532 ,  H01L21/02579 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66515 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: Integrated circuit structures having source or drain structures and germanium N-channels are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion, the upper fin portion including germanium. A gate stack is over the upper fin portion of the fin. A first source or drain structure includes an epitaxial structure embedded in the fin at a first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at a second side of the gate stack. Each epitaxial structure includes a first semiconductor layer in contact with the upper fin portion, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer comprises silicon, germanium and phosphorous, and the second semiconductor layer comprises silicon and phosphorous.

公开(公告)号：US11955334B2

公开(公告)日：2024-04-09

申请号：US17129744

申请日：2020-12-21

Applicant: AZUR SPACE SOLAR POWER GMBH

Inventor： Gregor Keller ,  Clemens Waechter ,  Thorsten Wierzkowski

IPC: H01L21/02 ,  C23C16/30 ,  C30B25/14 ,  C30B29/42 ,  H01L29/06

CPC classification number: H01L21/02579 ,  C23C16/301 ,  C30B25/14 ,  C30B29/42 ,  H01L21/02546 ,  H01L21/02576 ,  H01L21/0262 ,  H01L29/06

Abstract: A vapor phase epitaxy method of growing a III-V layer with a doping profile that changes from a p-doping to an n-doping on a surface of a substrate or a preceding layer from the vapor phase from an epitaxial gas flow, at least one first precursor for an element of main group III, and at least one second precursor for an element of main group V. When a first growth height is reached, a first initial doping level is set by means of a ratio of a first mass flow of the first precursor to a second mass flow of the second precursor in the epitaxial gas flow, and subsequently, by stepwise or continuously changing the ratio of the first mass flow to the second mass flow and by stepwise or continuously increasing a mass flow of a third precursor for an n-type dopant in the epitaxial gas flow.

公开(公告)号：US11935951B2

公开(公告)日：2024-03-19

申请号：US17981639

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chun Hsiung Tsai ,  Yuan-Ko Hwang

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: The present disclosure provides a semiconductor device structure in accordance with some embodiments. In some embodiments, the semiconductor device structure includes a semiconductor substrate of a first semiconductor material and having first recesses. The semiconductor device structure further includes a first gate stack formed on the semiconductor substrate and being adjacent the first recesses. In some examples, a passivation material layer of a second semiconductor material is formed in the first recesses. In some embodiments, first source and drain (S/D) features of a third semiconductor material are formed in the first recesses and are separated from the semiconductor substrate by the passivation material layer. In some cases, the passivation material layer is free of chlorine.