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    Electronic system comprising a plurality of microprocessors
    1.
    发明授权
    Electronic system comprising a plurality of microprocessors 有权

    公开(公告)号：US12058255B2

    公开(公告)日：2024-08-06

    申请号：US17553481

    申请日：2021-12-16

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grand Ouest) SAS

    Inventor： Julien Couvrand ,  William Orlando

    IPC: H04L9/08

    CPC classification number: H04L9/0894

    Abstract: The present description concerns an electronic system including one or a plurality of first microprocessors, a second microprocessor for securely managing first encryption keys of the first microprocessors, the second microprocessor being configured to communicate with each first microprocessor and including a first non-volatile memory having at least one second key stored therein, and for each first microprocessor, a second non-volatile memory external to the second microprocessor and containing the first keys of the first microprocessor encrypted with the second key.

    Modification of a memory of a secure microprocessor
    2.
    发明授权
    Modification of a memory of a secure microprocessor 有权

    公开(公告)号：US11340798B2

    公开(公告)日：2022-05-24

    申请号：US16898921

    申请日：2020-06-11

    Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics (Grand Ouest) SAS

    Inventor： William Orlando ,  Julien Couvrand ,  Pierre Guillemin

    IPC: G06F3/06 ,  H04L9/06

    Abstract: A method includes receiving, by a first microprocessor, a request of modification of a content of a first memory of the first microprocessor, the first memory being accessible only by the first microprocessor. The method includes accessing, by the first microprocessor, first data associated with the request and a signature generated from the first data with an asymmetric cipher algorithm. The first data and the signature are available in a second memory of a second microprocessor, and the first data is representative of a modification to be applied to the content of the first memory. The modification is representative of a modification of a set of services exposed by the first microprocessor. The method includes verifying, by the first microprocessor, authenticity of the first data based on the signature; and modifying the content of the first memory according to the first data, the modifying being conditioned by the verifying.

    Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes
    3.
    发明授权
    Stack overflow protection by monitoring addresses of a stack of multi-bit protection codes 有权

    公开(公告)号：US11113384B2

    公开(公告)日：2021-09-07

    申请号：US15847827

    申请日：2017-12-19

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pierre Guillemin ,  William Orlando

    IPC: G06F21/52 ,  G06F9/00

    Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in an internal memory coupled to the processing unit. Comparators in the hardware monitor circuit are arranged to accept values from the internal memory and gating logic coupled to the comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.

    HARDWARE MONITOR OF A PROCESSING UNIT STACK STRUCTURE
    5.
    发明申请
    HARDWARE MONITOR OF A PROCESSING UNIT STACK STRUCTURE 审中-公开

    公开(公告)号：US20180181748A1

    公开(公告)日：2018-06-28

    申请号：US15847827

    申请日：2017-12-19

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Pierre Guillemin ,  William Orlando

    IPC: G06F21/52

    CPC classification number: G06F21/52 ,  G06F2221/2123 ,  G06F2221/2153

    Abstract: A hardware monitor circuit includes an electronic control circuit coupled to a processing unit. The electronic control circuit generates multi-bit protection codes and directs operations of the hardware monitor circuit. A bus interface is coupled to an address bus of the processing unit, and the bus interface passes signals associated with a stack structure of the processing unit. The stack structure is arranged to store the multi-bit protection codes in at least one internal memory coupled to the processing unit. A plurality of comparators in the hardware monitor circuit are arranged to accept values from the at least one internal memory and gating logic coupled to the plurality of comparators is arranged to generate an error signal when it detects that an address on the address bus read via the bus interface is equal to an address stored in the at least one internal memory. Upon generating the error signal, the processing unit is placed in a secure mode.

    METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT
    9.
    发明申请
    METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT 审中-公开

    公开(公告)号：US20200319247A1

    公开(公告)日：2020-10-08

    申请号：US16909696

    申请日：2020-06-23

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

    IPC: G01R31/317 ,  G06F11/22 ,  G06F9/4401 ,  G06F11/36 ,  G06F21/75 ,  G06F21/62

    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

    METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT
    10.
    发明申请
    METHOD FOR MANAGING A RETURN OF A PRODUCT FOR ANALYSIS AND CORRESPONDING PRODUCT 审中-公开

    公开(公告)号：US20190107576A1

    公开(公告)日：2019-04-11

    申请号：US16155953

    申请日：2018-10-10

    Applicant: STMicroelectronics (Rousset) SAS

    Inventor： Lionel Sinegre ,  Eric Sagnard ,  Stephan Courcambeck ,  William Orlando ,  Layachi Daineche

    IPC: G01R31/317 ,  G06F11/36 ,  G06F9/4401 ,  G06F11/22

    Abstract: A method for managing a product includes: placing an integrated circuit in a bootstrap mode with debugging prohibition in response to each reset or power-up of the integrated circuit and in an absence of a reception, on a test access port of the product, of a first command; and placing the integrated circuit in an analysis mode with debugging authorization in response to reception, on the test access port, of the first command following the reset or the power-up of the integrated circuit. Placing the integrated circuit in the analysis mode is maintained at least as long as a second command has not been received on the test access port. Placing the integrated circuit in the bootstrap mode and placing the integrated circuit in the analysis mode are performed in response to a determination that the integrated circuit has never before been placed in the analysis mode with debugging authorization.

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