公开(公告)号：US20210217746A1

公开(公告)日：2021-07-15

申请号：US17143703

申请日：2021-01-07

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie ARNAUD ,  Severine LEBRETTE

IPC: H01L27/02 ,  H01L21/22 ,  H01L29/66 ,  H01L29/866

Abstract: ESD protection devices and methods are provided. In at least one embodiment, a device includes a first stack that forms a Zener diode. The first stack includes a substrate of a first conductivity type having a first region of a second conductivity type located therein. The first area is flush with a surface of the substrate. A second stack forms a diode and is located on and in contact with the surface of the substrate. The second stack includes a first layer of the second conductivity type having a second region of the first conductivity type located therein. The second area is flush, opposite the first stack, with the surface of the first layer. A third stack includes at least a second layer made of an oxygen-doped material, on and in contact with the second stack.

公开(公告)号：US20200185378A1

公开(公告)日：2020-06-11

申请号：US16709753

申请日：2019-12-10

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie ARNAUD

IPC: H01L27/07 ,  H01L27/02

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.

公开(公告)号：US20240021701A1

公开(公告)日：2024-01-18

申请号：US18349041

申请日：2023-07-07

Applicant: STMicroelectronics (Tours) SAS

Inventor： Aurelie ARNAUD ,  Julien LADROUE

IPC: H01L29/66 ,  H01L29/866 ,  H01L29/861

CPC classification number: H01L29/66106 ,  H01L29/866 ,  H01L29/8611 ,  H01L29/66128 ,  H01L29/66136 ,  H01L21/02315

Abstract: The present description concerns a method for manufacturing a protection device against overvoltages, comprising the following successive steps: a) epitaxially forming, on a semiconductor substrate, a semiconductor layer; b) submitting the upper surface of the semiconductor layer to a fluorinated-plasma process; and c) forming an electrically-insulating layer over and contacting the upper surface of the semiconductor layer.

公开(公告)号：US20230089468A1

公开(公告)日：2023-03-23

申请号：US18053722

申请日：2022-11-08

Applicant: STMICROELECTRONICS (TOURS) SAS

Inventor： Aurelie ARNAUD

IPC: H01L27/07 ,  H01L27/02

Abstract: The present disclosure concerns a switching device comprising a first phosphorus-doped silicon layer on top of and in contact with a second arsenic-doped silicon layer. The present disclosure also concerns a method of making a switching device that includes forming a phosphorus-doped silicon layer in an arsenic-doped silicon layer.