公开(公告)号：US10530348B2

公开(公告)日：2020-01-07

申请号：US16273317

申请日：2019-02-12

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh ,  Yi Ren Chin

IPC: G11C7/22 ,  H03K5/151 ,  G11C19/28 ,  H03L7/00

Abstract: An electronic device includes clock generation circuitry. The clock generation circuitry includes a first flip flop receiving as input a device clock and being triggered by an input clock and a second flip flop receiving, as input, output from the first flip flop and being triggered by the input clock. A first inverter receives output from the first flip flop as input and a second inverter receives output from the second flip flop as input. A first AND gate receives, as input, output from the second flip flop and the first inverter, and generates a first clock as output. A second AND gate receives, as input, output from the first flip flop and the second inverter, and generates a second clock as output.

公开(公告)号：US10243545B2

公开(公告)日：2019-03-26

申请号：US15425277

申请日：2017-02-06

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh ,  Yi Ren Chin

IPC: H03L5/00 ,  H03K5/151 ,  G11C19/28 ,  H03L7/00 ,  G11C7/22

Abstract: Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.

公开(公告)号：US20180226957A1

公开(公告)日：2018-08-09

申请号：US15425277

申请日：2017-02-06

Applicant: STMicroelectronics Asia Pacific Pte Ltd

Inventor： Beng-Heng Goh ,  Yi Ren Chin

IPC: H03K5/151 ,  G11C19/28 ,  H03K3/3562 ,  H03L7/00

CPC classification number: H03K5/1515 ,  G11C7/22 ,  G11C7/222 ,  G11C19/28 ,  G11C19/287 ,  H03L7/00

Abstract: Disclosed herein is an electronic device including a flip flop and clock generation circuitry for controlling the flip flop. The flip flop includes a master latch receiving input for the flip flop, with the master latch latching the received input to its output in response to a first clock. The slave latch receives input from the output of the master latch, and latches the received input to its output in response to a second clock. The clock generation circuitry is configured to logically combine a device clock and an input clock to produce the first and second clocks.