公开(公告)号：US12184289B2

公开(公告)日：2024-12-31

申请号：US18492597

申请日：2023-10-23

Applicant: STMicroelectronics France

Inventor： Lionel Vogt

IPC: H03K5/00

Abstract: In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

公开(公告)号：US20240178817A1

公开(公告)日：2024-05-30

申请号：US18520167

申请日：2023-11-27

Applicant: STMicroelectronics France

Inventor： Eric Andre ,  Lionel Vogt

IPC: H03H11/04 ,  H03K3/037 ,  H03K17/687 ,  H04B1/04

CPC classification number: H03H11/04 ,  H03K3/037 ,  H03K17/6871 ,  H04B1/04

Abstract: In embodiments, a radio frequency transmitter comprising at least one filtering circuit is provided. The filtering circuit includes a series/parallel shift register comprising a binary input and N binary outputs, with N being an integer greater than or equal to OSR, OSR being an integer greater than or equal to 2. The binary outputs ranging from 0 to N−1, the register receiving a binary data signal at a data frequency on its input and implementing shifts on the N binary outputs at a frequency equal to a multiplier of the data frequency and OSR. The filtering circuit further comprising a first circuit defined by N coefficients Ci. For each non-zero coefficient Ci, a signal determined by the coefficient Ci and by the corresponding one of the binary outputs. The filtering circuit further comprising and an adder circuit delivering an output equal to the sum of analog signals.