公开(公告)号：US08854095B2

公开(公告)日：2014-10-07

申请号：US13674394

申请日：2012-11-12

Applicant: STMicroelectronics International N. V.

Inventor： Amit Katyal

IPC: H03L7/06 ,  H03L7/08 ,  H03B19/00

CPC classification number: H03L7/0891 ,  H03L7/095 ,  H03L7/101 ,  H03L7/104 ,  H03L7/187 ,  H03L7/235

Abstract: A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.

Abstract translation: 锁相环（PLL）电路包含开关电容电路和反馈电路，以减少实现锁定状态的时间。 在第一模式中，使用压控振荡器（VCO）的频率来调节VCO的控制电压以实现粗略的锁定状态。 在第二模式中，使用参考频率来控制电荷泵以更精确地调整控制电压以实现PLL的精细锁定。 由于VCO频率明显高于参考频率，所以在第一模式期间，控制电压以更大的速率变化。 在一些实施例中，可以通过将VCO控制电压初始化为特定电压来进一步降低实现锁定的时间，以便在粗略地减小启动时的控制电压与第一模式开始时的控制电压之间的差异 锁。