公开(公告)号：US20240377539A1

公开(公告)日：2024-11-14

申请号：US18651950

申请日：2024-05-01

Applicant: STMicroelectronics International N. V.

Inventor： Olivier Lemarchand ,  Ulysse Gaffet ,  Robin Vassal

IPC: G01S17/894 ,  G02B27/00 ,  G06V10/82

Abstract: The present disclosure relates to a system includes a microcontroller including a neural network, a time-of-flight sensor including a plurality of pixels and configured to perform a capture of a scene comprising a user, the capture comprising, for each pixel, the measurement of a distance from the user and of a signal value. The sensor is further configured to calculate a value of a standard deviation associated with the distance value, and a value of a standard deviation associated with the signal value and a confidence value. The sensor is further configured to provide the values to the neural network. The neural network is configured to generate, based on the values, an estimate of a direction associated with the user. The system further includes a display, the microcontroller is configured to control the display, or another circuit, based on the estimate.

公开(公告)号：US20240330692A1

公开(公告)日：2024-10-03

申请号：US18612257

申请日：2024-03-21

Applicant: STMicroelectronics International N. V.

Inventor： He Huang ,  Basile Wolfrom

IPC: G06N3/09

CPC classification number: G06N3/09

Abstract: According to one aspect, a method for searching, using a computer, for an optimal combination of hyperparameters allows an automatic learning model to be defined. The method includes several hyperparameter combination tests, each hyperparameter combination test including cross-validation, using a validation data set, the cross-validation defining several performance tests, each hyperparameter combination test being stopped if a performance test score is lower than a best score, the cross-validation further including updating the best score when all of the performance scores computed for this cross-validation are higher than the best score, the updated best score then corresponding to the lowest performance score from among the set of performance scores computed for this cross-validation.

公开(公告)号：US20240120933A1

公开(公告)日：2024-04-11

申请号：US18371723

申请日：2023-09-22

Applicant: STMicroelectronics International N. V.

Inventor： Sandrine NICOLAS ,  Danika PERRIN ,  Jean-Baptiste CASANOVA

IPC: H03M1/38

CPC classification number: H03M1/38

Abstract: The present description concerns a method of controlling an analog-to-digital converter, wherein most significant bits are determined by successive approximations implementing a first digital-to-analog converter and a second digital-to-analog converter. Further, least significant bits are determined by a time-to-digital conversion by applying a first ramp to the output of the first converter with a third digital-to-analog converter and by applying a second ramp to the output of the second converter with a fourth digital-to-analog converter. The variation direction of the first and second ramps is determined by the comparison of the outputs of the first and second converters at the end of the successive approximations.

公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US08854095B2

公开(公告)日：2014-10-07

申请号：US13674394

申请日：2012-11-12

Applicant: STMicroelectronics International N. V.

Inventor： Amit Katyal

IPC: H03L7/06 ,  H03L7/08 ,  H03B19/00

CPC classification number: H03L7/0891 ,  H03L7/095 ,  H03L7/101 ,  H03L7/104 ,  H03L7/187 ,  H03L7/235

Abstract: A phase lock loop (PLL) circuit incorporates switched capacitive circuitry and feedback circuitry to reduce the time to achieve a lock condition. During a first mode, the frequency of a voltage controlled oscillator (VCO) is used to adjust the control voltage of the VCO to achieve a coarse lock condition. During a second mode, a reference frequency is used to control a charge pump to more precisely adjust the control voltage to achieve fine lock of the PLL. Because the VCO frequency is significantly higher than the reference frequency, the control voltage is varied at a greater rate during the first mode. In some embodiments, the time to achieve lock may be further reduced by initializing the VCO control voltage to a particular voltage so as to reduce the difference between the control voltage at start-up and the control voltage at the beginning of the first mode during coarse lock.

Abstract translation: 锁相环（PLL）电路包含开关电容电路和反馈电路，以减少实现锁定状态的时间。 在第一模式中，使用压控振荡器（VCO）的频率来调节VCO的控制电压以实现粗略的锁定状态。 在第二模式中，使用参考频率来控制电荷泵以更精确地调整控制电压以实现PLL的精细锁定。 由于VCO频率明显高于参考频率，所以在第一模式期间，控制电压以更大的速率变化。 在一些实施例中，可以通过将VCO控制电压初始化为特定电压来进一步降低实现锁定的时间，以便在粗略地减小启动时的控制电压与第一模式开始时的控制电压之间的差异 锁。