公开(公告)号：US11513883B2

公开(公告)日：2022-11-29

申请号：US17161832

申请日：2021-01-29

Applicant: STMicroelectronics International N.V.

Inventor： Charul Jain ,  Asif Rashid Zargar

IPC: G06F11/07

Abstract: An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

公开(公告)号：US12190120B2

公开(公告)日：2025-01-07

申请号：US18312237

申请日：2023-05-04

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Roberto Colombo

IPC: G06F9/4401 ,  G06F21/64

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

公开(公告)号：US12229253B2

公开(公告)日：2025-02-18

申请号：US17340164

申请日：2021-06-07

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics International N.V.

Inventor： Asif Rashid Zargar ,  Gilles Eyzat ,  Charul Jain

IPC: G06F21/55

Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

公开(公告)号：US20220245011A1

公开(公告)日：2022-08-04

申请号：US17161832

申请日：2021-01-29

Applicant: STMicroelectronics International N.V.

Inventor： Charul Jain ,  Asif Rashid Zargar

IPC: G06F11/07

Abstract: An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

公开(公告)号：US20150358300A1

公开(公告)日：2015-12-10

申请号：US14645688

申请日：2015-03-12

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ignazio Antonino URZI ,  Asif Rashid Zargar

IPC: H04L29/06

CPC classification number: H04L63/0464 ,  G06F12/1408 ,  G06F21/71 ,  G06F21/79 ,  H04L9/0618 ,  H04L63/061

Abstract: A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.

Abstract translation: 一种用于管理分别属于多个信道的多个存储器的加密存储体中根据交错寻址方案物理地实现的加密的全局交错存储器空间的操作的方法。 该方法包括向每个信道提供本地地址指针，该本地地址指针被配置成每当在指针指向的当前地址处寻址全局存储空间时，沿着全局存储器空间递增地移动，并且在局部指针的移动 在通过与当前地址的特定事务进行地址交织的情况下，从信道寻址全局存储器空间，以及在由信道发起的特定事务的信道的接收时，重新加密位于 当前地址使用新的加密密钥，并将本地地址指针递增到其下一个位置。

公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

Inventor： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC: G11C7/24 ,  G11C7/10

CPC classification number: G11C7/24 ,  G11C7/1039 ,  G11C7/1069

Abstract: In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US20230409341A1

公开(公告)日：2023-12-21

申请号：US18312237

申请日：2023-05-04

Applicant: STMicroelectronics Application GMBH ,  STMicroelectronics International N.V.

Inventor： Asif Rashid Zargar ,  Roberto Colombo

IPC: G06F9/4401 ,  G06F21/64

CPC classification number: G06F9/4405 ,  G06F21/64

Abstract: In embodiments, a reset management circuit executes reset, configuration, and software runtime phases when a processing system is switched on, where one or more microprocessors start at respective start addresses. During the configuration phase, a circuit reads a boot record from a non-volatile memory and stores it to registers. The circuit sequentially reads data records of configuration data from the non-volatile memory and generates a write request for each data record to store the data of the respective data record to a second circuit with associated address data indicated in the respective data record. The processing system processes the boot record and boot configuration data provided by the second circuits to selectively start a predetermined microprocessor at a default start address or at a start address indicated by the boot configuration data, or start one or more microprocessors at respective start addresses as indicated by the boot record.

公开(公告)号：US20210390180A1

公开(公告)日：2021-12-16

申请号：US17340164

申请日：2021-06-07

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics International N.V.

Inventor： Asif Rashid Zargar ,  Gilles Eyzat ,  Charul Jain

IPC: G06F21/55

Abstract: A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

公开(公告)号：US09419952B2

公开(公告)日：2016-08-16

申请号：US14645688

申请日：2015-03-12

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Ignazio Antonino Urzi ,  Asif Rashid Zargar

IPC: H04L29/06 ,  G06F12/14 ,  G06F21/72 ,  H04N7/16 ,  H04L9/06

CPC classification number: H04L63/0464 ,  G06F12/1408 ,  G06F21/71 ,  G06F21/79 ,  H04L9/0618 ,  H04L63/061

Abstract: A method for managing an operation of an encrypted global interleaved memory space physically implemented according to an interleaving addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels. The method includes providing each channel with a local address pointer configured to be incrementally moved along the global memory space each time the global memory space is addressed at the current address pointed by the pointer, and in an absence of movement of the local pointer of a channel during a time period, addressing the global memory space from the channel through the address interleaving with a specific transaction at the current address, and upon reception at the channel of the specific transaction having been initiated by the channel, re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to its next position.

Abstract translation: 一种用于管理分别属于多个信道的多个存储器的加密存储体中根据交错寻址方案物理地实现的加密的全局交错存储器空间的操作的方法。 该方法包括向每个信道提供本地地址指针，该本地地址指针被配置成每当在指针指向的当前地址处寻址全局存储空间时，沿着全局存储器空间递增地移动，并且在局部指针的移动 在通过与当前地址的特定事务进行地址交织的情况下，从信道寻址全局存储器空间，以及在由信道发起的特定事务的信道的接收时，重新加密位于 当前地址使用新的加密密钥，并将本地地址指针递增到其下一个位置。