公开(公告)号：US12068057B2

公开(公告)日：2024-08-20

申请号：US18056803

申请日：2022-11-18

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N.V. ,  STMicroelectronics Application GMBH

发明人： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC分类号： G11C7/24 ,  G11C7/10

CPC分类号： G11C7/24 ,  G11C7/1039 ,  G11C7/1069

摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US20230170006A1

公开(公告)日：2023-06-01

申请号：US18056803

申请日：2022-11-18

申请人： STMicroelectronics S.r.l. ,  STMicroelectronics International N. V. ,  STMicroelectronics Application GMBH

发明人： Asif Rashid Zargar ,  Nicolas Bernard Grossier ,  Charul Jain ,  Roberto Colombo

IPC分类号： G11C7/24 ,  G11C7/10

CPC分类号： G11C7/24 ,  G11C7/1039 ,  G11C7/1069

摘要： In an embodiment a processing system includes a plurality of storage elements, each storage element comprising a latch or a flip-flop and being configured to receive a write request comprising a data bit and to store the received data bit to the latch or the flip-flop, a non-volatile memory configured to store data bits for the plurality of storage elements, a hardware configuration circuit configured to read the data bits from the non-volatile memory and generate write requests in order to store the data bits to the storage elements and a hardware circuit configured to change operation as a function of a logic level stored to a latch or a flip-flop of a first storage element of the plurality of storage elements, wherein the first storage element comprises a further latch or a further flip-flop and is configured to store, in response to the write request, an inverted version of the received data bit to the further latch or the further flip-flop.

公开(公告)号：US11513883B2

公开(公告)日：2022-11-29

申请号：US17161832

申请日：2021-01-29

申请人： STMicroelectronics International N.V.

发明人： Charul Jain ,  Asif Rashid Zargar

IPC分类号： G06F11/07

摘要： An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.

公开(公告)号：US20210390180A1

公开(公告)日：2021-12-16

申请号：US17340164

申请日：2021-06-07

申请人： STMicroelectronics (Alps) SAS ,  STMicroelectronics International N.V.

发明人： Asif Rashid Zargar ,  Gilles Eyzat ,  Charul Jain

IPC分类号： G06F21/55

摘要： A system on a chip comprising a set of one-time programmable memory elements that comprises a first valid configuration; a second valid configuration; and a plurality of invalid configurations. The system on a chip also comprises a programming indicator initially comprising a first value and configured to be permanently set to a second value. The system on a chip further comprises a decoder circuit in communication with the set of one-time programmable memory elements to determine whether the set of one-time programmable memory elements is in the first valid configuration, the second valid configuration, or any one of the plurality of invalid configurations. The decoder circuit generates a threat-detection signal when the set of one-time programmable memory elements is in any of the plurality of invalid configurations when the programming indicator is permanently set to the second value.

公开(公告)号：US20220245011A1

公开(公告)日：2022-08-04

申请号：US17161832

申请日：2021-01-29

申请人： STMicroelectronics International N.V.

发明人： Charul Jain ,  Asif Rashid Zargar

IPC分类号： G06F11/07

摘要： An apparatus includes a primary processor and a secondary processor configured to receive a first signal, a second signal and a plurality of input signals, and perform same operations as each other based on the first signal, the second signal and the plurality of input signals, a comparison circuit configured to receive output signals of the primary processor and the secondary processor, and detect a lockstep mismatch between the primary processor and the secondary processor based on the output signals, a fault capturing circuit configured to receive the first signal and the second signal, and capture a fault signal generated by the comparison circuit, and a first glitch absorption device configured to receive the first signal and the second signal, and absorb glitches fed into the first glitch absorption device.