公开(公告)号：US20240413043A1

公开(公告)日：2024-12-12

申请号：US18207918

申请日：2023-06-09

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  Laurent Schwartz ,  Ludovic Fourneaud

IPC: H01L23/373 ,  H01L21/48 ,  H01L23/367

Abstract: Systems, apparatuses, and method for nanowires for semiconductor packages are provided herein. The semiconductor package may include die attached to a substrate. A lid may also be attached to the substrate. The die includes die nanowires and the lid includes lid nanowires. The nanowires may be formed over the entirety of the die or in a pattern. The lid may have a corresponding or symmetrical coverage or pattern. In the semiconductor package, the die nanowires and the lid nanowires are coupled to, among other things, provide improved heat dissipation.

公开(公告)号：US20240321809A1

公开(公告)日：2024-09-26

申请号：US18601216

申请日：2024-03-11

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  David AUCHERE ,  Vipin VELAYUDHAN

IPC: H01L23/00

CPC classification number: H01L24/32 ,  H01L24/27 ,  H01L24/29 ,  H01L2224/27318 ,  H01L2224/2741 ,  H01L2224/29144 ,  H01L2224/29155 ,  H01L2224/32227 ,  H01L2224/32238 ,  H01L2924/151

Abstract: An integrated circuit chip is bonded to a support. The chip includes a first connection pad and two second connection pads. The support includes a third connection pad and two fourth connection pads. A stack layers includes first, second, and third conductive layers and insulating layers. The first, second, and third conductive layers are separated from one another by the insulating layers. The second conductive layer is positioned between the first and third conductive layers. The first and third conductive layers electrically connect the two second connection pads to the two fourth connection pads. The second conductive layer electrically connects the first connection pad to the third connection pad.

公开(公告)号：US20240186679A1

公开(公告)日：2024-06-06

申请号：US18526427

申请日：2023-12-01

Applicant: STMicroelectronics International N.V.

Inventor： Romain COFFY ,  Laurent SCHWARTZ ,  Ludovic FOURNEAUD

IPC: H01Q1/22 ,  H01L21/56 ,  H01L23/31 ,  H05K1/02

CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/3121 ,  H05K1/0237 ,  H01L24/16 ,  H05K2201/10098

Abstract: A waveguide has a first input/output for receiving/outputting a radio frequency (RF) wave and guiding the RF wave between the first input/output and a second input/output. An electronic integrated circuit chip is electrically connected at a front face to a metal level of a carrier substrate which includes a patch antenna. An electrically insulating embedding material surrounds the electronic chip and is disposed between the patch antenna and the first input/output of the waveguide which is at least in contact with the embedding material. The electronic chip cooperates electrically with the patch antenna so as to cause the patch antenna to transmit the RF wave to the first input/output through the embedding material. The electronic chip also processes an electrical signal from the patch antenna in response to the patch antenna receiving the radio frequency wave output by the first input/output via the embedding material.