公开(公告)号：US20240361791A1

公开(公告)日：2024-10-31

申请号：US18139786

申请日：2023-04-26

Applicant: STMicroelectronics International N.V.

Inventor： Federico MUSARRA ,  Sandor PETENYI

IPC: G05F1/575 ,  G05F1/565 ,  G05F3/24

CPC classification number: G05F1/575 ,  G05F1/565 ,  G05F3/24

Abstract: An electronic device includes multiple integrated circuits, each containing a power transistor connected between an input voltage node and a load node, as well as a regulation circuit generating at least one sense current representing the output current of the power transistor. The regulation circuits modulate the output currents of their power transistors based on a value derived from the sense currents generated by the regulation circuits of other integrated circuits. This derived value can be based on an average of the sense currents generated by the regulation circuits or on one of the sense currents. In particular, the integrated circuits can be arranged in a daisy-chained relationship, allowing each regulation circuit to compare its sense current with the one from the immediately preceding circuit, except for the first regulation circuit, which compares its sense current with the last circuit's sense current in the chain.

公开(公告)号：US20240402241A1

公开(公告)日：2024-12-05

申请号：US18203737

申请日：2023-05-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandor PETENYI ,  Lukas BURIAN

IPC: G01R31/28 ,  G01R27/08

Abstract: Disclosed herein is a testing circuit for indirectly testing generation of a power-on-reset signal within an integrated circuit (IC). The testing circuit includes a switch configured to selectively disconnect an internal circuit from a test pin of the IC in response to start-up of the IC, a plurality of resistors connected between the test pin and a respective plurality of switches that are configured to selectively connect ones of the plurality of resistors to ground in response to corresponding control signals, and a control circuit configured to produce, at the test pin, a resistance indicative of status of generation of the POR signal by selectively operating the plurality of switches based upon statuses of a plurality of signals from which the POR signal is generated.

公开(公告)号：US20250079824A1

公开(公告)日：2025-03-06

申请号：US18242621

申请日：2023-09-06

Applicant: STMicroelectronics International N.V.

Inventor： Sandor PETENYI ,  Lukas MACHACEK ,  Salvatore D'ANGELO

IPC: H02H3/20 ,  G01R31/74

Abstract: Disclosed herein is method for fault detection and communication in analog power electronic circuits with a multiplicity of electronic fuses (e.g., a primary fuse and at least one secondary fuse). Current flow is monitored through each fuse. Fault conditions in these electronic fuses are identified. Upon detection, the fault signaling line, which is common to all fuses, is driven to a voltage indicative of the detected fault condition. The primary electronic fuse then latches the voltage on this fault signaling line. A detection and communication circuit enables corrective actions to be performed at the fuse level, dictated by the latched voltage.

公开(公告)号：US20250080100A1

公开(公告)日：2025-03-06

申请号：US18240585

申请日：2023-08-31

Applicant: STMicroelectronics International N.V.

Inventor： Sandor PETENYI ,  Lukas BURYANEC

IPC: H03K17/082 ,  H03K5/24

Abstract: A power circuit includes a power transistor coupled between input and output nodes and receiving a control signal. A current sensing current senses a power current provided by the power transistor to the output node and generates a sense voltage. A voltage sensing circuit senses a drain-to-source voltage of the power transistor and generates a VDS sense current. A safe operating area (SOA) shaping circuit has a gain set by an adjustable resistance that is dynamically adjusted based upon the VDS sense current, the SOA shaping circuit applying the gain to the sense voltage to produce an adjusted sense voltage. A timing circuit generates an intermediate voltage by comparing the adjusted sense voltage and a first reference. An output comparator asserts a flag in response to the intermediate voltage becoming at least equal to a second reference. The control signal is modified in response to assertion of the flag.