公开(公告)号：US20220345149A1

公开(公告)日：2022-10-27

申请号：US17723225

申请日：2022-04-18

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20230061509A1

公开(公告)日：2023-03-02

申请号：US17876263

申请日：2022-07-28

Applicant: STMicroelectronics International N.V.

Inventor： Sharad GUPTA ,  Ankur BAL

IPC: H03M1/06

Abstract: A data weighted averaging (DWA) data word in a standard or normal form unary code format is first converted to a thermometer control word in an alternative or spatial form unary code format. The thermometer control word is then converted from the alternative or spatial form unary code format to output a corresponding binary word.

公开(公告)号：US20210351780A1

公开(公告)日：2021-11-11

申请号：US17306178

申请日：2021-05-03

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sharad GUPTA

IPC: H03M1/08 ,  H03M1/06 ,  H03M1/10

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

公开(公告)号：US20240235573A1

公开(公告)日：2024-07-11

申请号：US18396542

申请日：2023-12-26

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Abhishek JAIN ,  Sharad GUPTA

IPC: H03M3/00

CPC classification number: H03M3/378 ,  H03M3/46 ,  H03M3/496

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

公开(公告)号：US20230054364A1

公开(公告)日：2023-02-23

申请号：US17982242

申请日：2022-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sharad GUPTA

IPC: H03M1/08 ,  H03M1/10 ,  H03M1/06

Abstract: An estimate of unit current element mismatch error in a digital to analog converter circuit is obtained through a correlation process. Unit current elements of the digital to analog converter circuit are actuated by bits of a thermometer coded signal generated in response to a quantization output signal. A correlation circuit generates the estimates of the unit current element mismatch error from a correlation of a first signal derived from the thermometer coded signal and a second signal derived from the quantization output signal.

公开(公告)号：US20250068538A1

公开(公告)日：2025-02-27

申请号：US18766904

申请日：2024-07-09

Applicant: STMicroelectronics International N.V.

Inventor： Sharad GUPTA ,  Ankur BAL

IPC: G06F11/34 ,  G01R31/28 ,  G06F11/30

Abstract: Various embodiments of the present disclosure disclose improved BIST systems and methods for testing digital devices. A method for testing a digital device includes receiving, based at least in part on an input signal, an output signal from a device under testing (DUT). The output signal is processed to generate a noise signal and a recovered signal for the DUT. The controller may generate a signal to noise power ratio based at least in part on the noise and recovered signals and compare the signal to noise power ratio to a predetermined power threshold to generate a performance metric.

公开(公告)号：US20230259158A1

公开(公告)日：2023-08-17

申请号：US18165855

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Ankur BAL ,  Sharad GUPTA ,  Anupam JAIN

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/08

Abstract: An integrated circuit includes a first subsystem including a first clock generator configured to generate a first clock signal. The integrated circuit also includes a second subsystem including a second clock generator configured to generate a second clock signal. The first subsystem includes an edge detector configured to detect an edge of the second clock signal. The first clock generator generates the first clock signal with a selected phase relative to the second clock signal based on the edge of the second clock signal.