公开(公告)号：US20130343137A1

公开(公告)日：2013-12-26

申请号：US14014208

申请日：2013-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Siddharth GUPTA ,  Nitin JAIN ,  Anand Kumar MISHRA

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。