公开(公告)号：US20240266343A1

公开(公告)日：2024-08-08

申请号：US18418051

申请日：2024-01-19

Applicant: STMicroelectronics International N.V.

Inventor： Anuj BHARDWAJ ,  Anand Kumar MISHRA ,  Rohit Kumar GUPTA

IPC: H01L27/02 ,  H01L21/762 ,  H01L23/538 ,  H01L29/06

CPC classification number: H01L27/0207 ,  H01L21/76224 ,  H01L23/5386 ,  H01L29/0607

Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.

公开(公告)号：US20220137133A1

公开(公告)日：2022-05-05

申请号：US17504139

申请日：2021-10-18

Applicant: STMicroelectronics International N.V.

Inventor： Rohit GOEL ,  Anand Kumar MISHRA ,  Rajnish GARG

IPC: G01R31/3185

Abstract: An integrated circuit includes a data propagation path including a flip-flop. The flip-flop includes a first latch and a second latch. The integrated circuit includes a third latch that acts as a dummy latch. The input of the third latch is coupled to the output of the first latch. The integrated circuit includes a fault detector coupled to the output of the flip-flop and the output of the third latch. The third latch includes a signal propagation delay selected so that the third latch will fail to capture data in a given clock cycle before the second latch of the flip-flop fails to capture the data in the given clock cycle. The fault detector that detects when the third latch is failed to capture the data.

公开(公告)号：US20130343137A1

公开(公告)日：2013-12-26

申请号：US14014208

申请日：2013-08-29

Applicant: STMicroelectronics International N.V.

Inventor： Siddharth GUPTA ,  Nitin JAIN ,  Anand Kumar MISHRA

IPC: G11C7/10

CPC classification number: G11C7/1096 ,  G11C7/18 ,  G11C7/22 ,  G11C8/12 ,  G11C8/18 ,  G11C11/413

Abstract: A memory architecture includes a plurality of local input and output circuitries, with each local input and output circuitry associated with at least one memory bank. The memory architecture also includes a global input and output circuitry, which includes a plurality of global sub-write circuitries, is coupled to the plurality of local input and output circuitries One global sub-write circuitry is enabled and provides a write-data to a selected local input and output circuitry.

Abstract translation: 存储器架构包括多个本地输入和输出电路，其中每个本地输入和输出电路与至少一个存储体相关联。 存储器架构还包括全局输入和输出电路，其包括多个全局子写入电路，耦合到多个本地输入和输出电路。一个全局子写入电路被使能，并将写入数据提供给 选择本地输入和输出电路。