公开(公告)号：US11552646B2

公开(公告)日：2023-01-10

申请号：US17354126

申请日：2021-06-22

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Vikram Singh

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

公开(公告)号：US12009830B2

公开(公告)日：2024-06-11

申请号：US18075977

申请日：2022-12-06

Applicant: STMicroelectronics International N.V.

Inventor： Ankur Bal ,  Vikram Singh

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/08 ,  H03M1/12

CPC classification number: H03M1/1023 ,  H03M1/0624 ,  H03M1/0836 ,  H03M1/1215

Abstract: A time-interleaved analog to digital converter (TI-ADC) includes a first sub-ADC configured to sample and convert an input analog signal to generate a first digital signal and a second sub-ADC configured to sample and convert said input analog signal to generate a second digital signal. Sampling by the second sub-ADC occurs with a time skew mismatch. A multiplexor interleaves the first and second digital signals to generate a third digital signal. A time skew mismatch error determination circuit processes the first and second digital signals to generate a time error corresponding to the time skew mismatch. A slope value of said third digital signal is determined and multiplied by the time error to generate a signal error. The signal error is summed with the third digital signal to generate a digital output signal which eliminates the error due to the time skew mismatch. This correction is performed in real time.

公开(公告)号：US20160109933A1

公开(公告)日：2016-04-21

申请号：US14516381

申请日：2014-10-16

Applicant: STMicroelectronics International N.V.

Inventor： Pratik Damle ,  Gaurav Mathur ,  Vikram Singh

IPC: G06F1/32

CPC classification number: G06F1/263 ,  G06F1/30 ,  G06F1/3203

Abstract: An embodiment is a circuit including a main power supply coupled to a first node, a charge reservoir coupled between a second node and ground, an isolation circuit coupled between the first node and the second node, and a plurality of secondary power supplies coupled to the second node, the plurality of secondary power supplies configured to receive power from the main power supply. The circuit further includes a detector circuit coupled to the first node, the detector circuit configured to detect the presence and absence of a first supply voltage at the first node, and a timing circuit coupled between the detector circuit and the plurality of secondary power supplies, the timing circuit configured to enable and disable the plurality of secondary power supplies in predetermined sequences based on the detection of the first supply voltage by the detector circuit.

Abstract translation: 一个实施例是一种电路，其包括耦合到第一节点的主电源，耦合在第二节点和地之间的电荷存储器，耦合在第一节点和第二节点之间的隔离电路，以及多个次电源， 第二节点，所述多个次级电源被配置为从主电源接收电力。 电路还包括耦合到第一节点的检测器电路，检测器电路被配置为检测在第一节点处是否存在第一电源电压，以及定时电路，耦合在检测器电路和多个次级电源之间， 所述定时电路被配置为基于所述检测器电路对所述第一电源电压的检测，以预定顺序启用和禁用所述多个次级电源。

公开(公告)号：US09690344B2

公开(公告)日：2017-06-27

申请号：US14516381

申请日：2014-10-16

Applicant: STMicroelectronics International N.V.

Inventor： Pratik Damle ,  Gaurav Mathur ,  Vikram Singh

IPC: G06F1/26 ,  G06F1/30 ,  G06F1/32

CPC classification number: G06F1/263 ,  G06F1/30 ,  G06F1/3203

Abstract: An embodiment is a circuit including a main power supply coupled to a first node, a charge reservoir coupled between a second node and ground, an isolation circuit coupled between the first node and the second node, and a plurality of secondary power supplies coupled to the second node, the plurality of secondary power supplies configured to receive power from the main power supply. The circuit further includes a detector circuit coupled to the first node, the detector circuit configured to detect the presence and absence of a first supply voltage at the first node, and a timing circuit coupled between the detector circuit and the plurality of secondary power supplies, the timing circuit configured to enable and disable the plurality of secondary power supplies in predetermined sequences based on the detection of the first supply voltage by the detector circuit.