CIRCUIT AND METHOD TO DETECT WORD-LINE LEAKAGE AND PROCESS DEFECTS IN NON-VOLATILE MEMORY ARRAY

    公开(公告)号:US20230008272A1

    公开(公告)日:2023-01-12

    申请号:US17837377

    申请日:2022-06-10

    Abstract: An integrated circuit die includes memory sectors, each memory sector including a memory array. The die includes a voltage regulator with a first transistor driven by an output voltage to thereby generate a gate voltage, the output voltage being generated based upon a difference between a constant current and a leakage current. A selection circuit selectively couples the gate voltage to a selected one of the plurality of memory sectors. A leakage detector circuit drives a second transistor with the output voltage to thereby generate a copy voltage based upon a difference between a variable current and a replica of the constant current, increases the variable current in response to the copy voltage being greater than the gate voltage, and asserts a leakage detection signal in response to the copy voltage being less than the gate voltage, the leakage detection signal indicating excess leakage within the memory array.

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