Non-switched capacitor offset voltage compensation in operational amplifiers
    1.
    发明申请
    Non-switched capacitor offset voltage compensation in operational amplifiers 有权
    运算放大器中的非开关电容失调电压补偿

    公开(公告)号:US20030214351A1

    公开(公告)日:2003-11-20

    申请号:US10356650

    申请日:2003-01-31

    CPC classification number: H03F3/45753

    Abstract: A method for reducing offset voltage in an operational amplifier without the need for switched-capacitors, includes introducing a tapped resistor chain between the common connected terminals of the transistors of the input differential pair of the operational amplifier and connecting the tail current source/sink of the differential amplifier to a selected tap of the resistor chain. The invention further provides an improved operational amplifier in accordance with the above method.

    Abstract translation: 一种用于减少运算放大器中的失调电压而不需要开关电容的方法包括在运算放大器的输入差分对的晶体管的公共连接端子之间引入分接电阻器链,并将尾电流源/ 差分放大器到电阻链的选定分接头。 本发明还提供了一种根据上述方法的改进的运算放大器。

    Switched-capacitor based charge redistribution successive approximation analog to digital converter (ADC)
    2.
    发明申请
    Switched-capacitor based charge redistribution successive approximation analog to digital converter (ADC) 审中-公开
    基于开关电容器的电荷再分配逐次逼近模数转换器(ADC)

    公开(公告)号:US20030063026A1

    公开(公告)日:2003-04-03

    申请号:US10255153

    申请日:2002-09-25

    Inventor: Tapas Nandy

    CPC classification number: H03M1/0854 H03M1/468 H03M1/804

    Abstract: An improved binary-weighted, switched-capacitor, charge-redistribution successive approximation analog-to-digital converter (ADC) may include an adjusting mechanism for adding a charge corresponding to one-half of the least significant bit (LSB) of the ADC to the charge stored in a switched capacitor array thereof after the sampling phase of the ADC. This is done to provide a quantization error that is evenly distributed between null0.5 times the LSB, without the need for any additional processing clock cycles.

    Abstract translation: 改进的二进制加权,开关电容器,电荷再分配逐次逼近模数转换器(ADC)可以包括调整机制,用于将对应于ADC的最低有效位(LSB)的一半的电荷加到 在ADC的采样相位之后存储在其开关电容器阵列中的电荷。 这是为了提供均匀分布在LSB的±0.5倍之间的量化误差,而不需要任何额外的处理时钟周期。

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