-
公开(公告)号：US20240223207A1
公开(公告)日：2024-07-04
申请号：US18148259
申请日：2022-12-29
Applicant: ROBERT BOSCH GMBH
Inventor： Kenneth Edward WOJCIECHOWSKI , Sangwoo LEE
IPC: H03M1/46 , G06F7/544 , G06F9/30 , G11C11/413 , H03M1/80
CPC classification number: H03M1/462 , G06F7/5443 , G06F9/3001 , G11C11/413 , H03M1/804 , G06F2207/4812 , G06F2207/4824
Abstract: A multiply-accumulate successive approximation (MASAR) column is provided. The MASAR column includes a plurality of MASAR cells, each including a multiplier configured to perform digital multiplication between an input activation received to an input and an operand to compute a result, and a unit capacitor configured to store the result as analog charge. The MASAR column further includes digital logic configured to perform analog summation of the analog charge of the unit capacitors of the plurality of MASAR cells to determine a digital output of the multiplication.
-
公开(公告)号：US11824549B2
公开(公告)日：2023-11-21
申请号：US17494494
申请日：2021-10-05
Applicant: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
Inventor： Junxi Chen , Zhengfeng Wang
CPC classification number: H03M1/0863 , G05F1/575 , G05F1/595 , H03F3/45475 , H03F3/505 , H03M1/46 , H03M1/804 , H03M1/38
Abstract: A reference voltage buffer circuit is provided, which could improve the reliability of the reference voltage buffer circuit, including: at least one output branch, where each output branch includes a delay control branch, a first MOSFET, and a second MOSFET; and a feedback branch, where in a first time period, the feedback branch is configured to output a first voltage to the delay control branch, and the delay control branch is configured to control the first MOSFET and the second MOSFET to be turned on, such that a source of the first MOSFET continuously outputs a reference voltage; and in a second time period, a voltage output from the feedback branch to the delay control branch is 0, the delay control branch is configured to control the second MOSFET to be turned off before the first MOSFET is turned off.
-
公开(公告)号：US10079610B2
公开(公告)日：2018-09-18
申请号：US15742435
申请日：2016-07-05
Applicant: Infineon Technologies AG
Inventor： Peter Bogner , Andreas Kalt , Jaafar Mejri , Martin Pernull
CPC classification number: H03M1/1071 , H03M1/109 , H03M1/12 , H03M1/468 , H03M1/804
Abstract: Representative implementations of devices and techniques provide a built-in self-test (BIST) for an analog-to-digital converter (ADC). Stimuli needed to test an ADC are generated within the chip containing the ADC. Evaluation circuitry is also available on-chip. Generation and evaluation circuits and systems are based on existing circuits and/or components of the chip.
-
4.发明申请公开(公告)号：US20180219558A1
公开(公告)日：2018-08-02
申请号：US15884018
申请日：2018-01-30
CPC classification number: H03M3/452 , G01R27/2605 , H03M1/002 , H03M1/08 , H03M1/1052 , H03M1/36 , H03M1/46 , H03M1/742 , H03M1/804 , H03M3/352 , H03M3/37 , H03M3/426 , H03M3/454 , H03M3/458
Abstract: A delta-sigma modulator. The delta-sigma modulator includes a loop filter (LF) and a digital-to-analog converter (DAC) connected to an input of the LF. The delta-sigma modulator also includes an asynchronous successive-approximation register (ASAR) quantizer (QTZ) connected to the DAC. The delta-sigma modulator also includes a second order noise coupling circuit (NC) connected to the ASAR and the DAC.
-
公开(公告)号：US10038452B2
公开(公告)日：2018-07-31
申请号：US15649313
申请日：2017-07-13
Applicant: Analog Devices, Inc.
Inventor： Baozhen Chen , Edward C. Guthrie , Michael C. W. Coln , Mark D. Maddox
CPC classification number: H03M1/0836 , H03M1/0651 , H03M1/0863 , H03M1/14 , H03M1/466 , H03M1/68 , H03M1/804 , H03M1/806
Abstract: During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.
-
Patent Agency Ranking
公开(公告)号：US10020734B2
公开(公告)日：2018-07-10
申请号：US15633688
申请日：2017-06-26
Applicant: Chengdu Monolithic Power Systems Co., Ltd.
Inventor： Changxian Zhong
IPC: G05F1/00 , H02M3/156 , H02M3/158 , H04W76/04 , H03K17/16 , H03M1/80 , H03M1/52 , H03M1/10 , H04W76/23 , H02M1/00
CPC classification number: H02M3/158 , H02M1/36 , H02M2001/0025 , H02M2001/0032 , H03K3/017 , H03K17/16 , H03M1/1014 , H03M1/1023 , H03M1/52 , H03M1/804 , H04W76/23
Abstract: An auto calibration method used in switching converters with constant on-time control. The auto calibration method includes: generating a periodical clock signal with a predetermined duty cycle; providing a first voltage and a second voltage to an on-time control circuit to generate an on-time control signal based on the first and second voltage; providing the clock signal and on-time control signal to a logic circuit to generate a switch control signal based on the clock signal and on-time control signal; comparing the duty cycle of the switch control signal with the duty cycle of the clock signal to adjust a calibration code signal; and adjusting circuit parameters of the on-time control circuit in accordance with the calibration code signal.
-
公开(公告)号：US20180152196A1
公开(公告)日：2018-05-31
申请号：US15799812
申请日：2017-10-31
Applicant: Avnera Corporation
Inventor： Jianping Wen , Garry Link , Wai Laing Lee
CPC classification number: H03M1/1009 , H03M1/0682 , H03M1/0692 , H03M1/38 , H03M1/403 , H03M1/462 , H03M1/468 , H03M1/804
Abstract: A system can include an analog input port; a digital output port; and a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC can include a voltage comparator Vd having a first input, a second input, and an output; a first plurality of capacitors Cp[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; a second plurality of capacitors Cn[0:n] that are coupled with the analog input port and each have a top plate and a bottom plate; and a SAR controller coupled between the output of the voltage comparator Vd and the digital output port.
-
8.发明申请公开(公告)号：US20180130606A1
公开(公告)日：2018-05-10
申请号：US15862992
申请日：2018-01-05
Applicant: Seiko Epson Corporation
Inventor： Atsushi TANAKA , Hideo HANEDA
CPC classification number: H01G4/40 , G01D5/56 , G01D21/00 , H03M1/001 , H03M1/1061 , H03M1/1245 , H03M1/38 , H03M1/468 , H03M1/68 , H03M1/804
Abstract: A capacitor circuit includes: a capacitor array including a plurality of capacitors; a switch array including a plurality of switch circuits, the switch circuits being respectively connected to the capacitors of the capacitor array; a plurality of switch control signal lines supplied with a plurality of switch control signals; and a substrate having a major surface on which the switch circuits are formed. At least part of the capacitors of the capacitor array is formed of a first conductive layer. The switch control signal lines are formed of a second conductive layer provided between the major surface and the first conductive layer. The capacitor array and the switch array are disposed so as to overlap each other at least in part in a plan view when viewed in a normal direction of the major surface.
-
9.发明授权公开(公告)号：US09935643B1
公开(公告)日：2018-04-03
申请号：US15453567
申请日：2017-03-08
Applicant: Marvell International Ltd.
Inventor： Nick C. Chang , Kenneth Thet Zin Oo , Wyant Chan , Pierte Roo
CPC classification number: H03M1/462 , H03M1/00 , H03M1/06 , H03M1/0695 , H03M1/12 , H03M1/80 , H03M1/804
Abstract: A successive-approximation register (SAR) analog-to-digital converter (ADC) includes a SAR circuit configured to generate a digital code based on an analog input signal. A digital-to-analog converter (DAC) is configured to convert the digital code to an analog voltage. The SAR circuit is further configured to generate a digital output signal based on a comparison between the analog input signal and the analog voltage. A first capacitor is configured to provide a reference voltage to the DAC. An adaptive charging module is configured to stabilize the reference voltage provided to the DAC by selectively connecting to a supply voltage during a first operating phase of the ADC to store a charge in the adaptive charging module and selectively connecting to the first capacitor during a second operating phase of the ADC to combine the charge stored in the adaptive charging module with a charge of the first capacitor.
-
公开(公告)号：US20180013441A1
公开(公告)日：2018-01-11
申请号：US15637073
申请日：2017-06-29
Applicant: Seiko Epson Corporation
Inventor： Hideo HANEDA
CPC classification number: H03M1/069 , H03M1/06 , H03M1/066 , H03M1/0697 , H03M1/46 , H03M1/468 , H03M1/682 , H03M1/804
Abstract: A circuit device includes a control circuit having a successive approximation register, a D/A conversion circuit adapted to perform D/A conversion on output data from the successive approximation register, and a comparison circuit adapted to compare an analog input signal and an output signal from the D/A conversion circuit with each other, the control circuit includes an upper limit value register and a lower limit value register adapted to respectively hold an upper limit value and a lower limit value of a conversion range, and increases the upper limit value or decreases the lower limit value in the case in which the same comparison result has been output by the comparison circuit a predetermined number of times or more.
-
-
-
-
-
-
-
-
-
Search Results
704
records
(took 0.033 seconds)
