公开(公告)号：US09000811B2

公开(公告)日：2015-04-07

申请号：US14199313

申请日：2014-03-06

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/00 ,  H03K17/04 ,  H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。

公开(公告)号：US20140266322A1

公开(公告)日：2014-09-18

申请号：US14199313

申请日：2014-03-06

Applicant: STMICROELECTRONICS R&D (SHANGHAI) CO. LTD.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/012

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。

公开(公告)号：US09000831B2

公开(公告)日：2015-04-07

申请号：US14073924

申请日：2013-11-07

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  KunKun Zheng

IPC: H03K17/687 ,  H03K17/10

CPC classification number: H03K17/102 ,  H03K2217/0054

Abstract: A pass gate circuit includes a first transistor coupled between an input node (receiving an input signal) and an output node (outputting an output signal). A second transistor is configured to generate a voltage difference in response to a bias current flowing therethrough, wherein that voltage difference is applied between a first gate of the first transistor and the output node. A differential amplifier functions to compare the voltage at the output node to a reference voltage and generate the bias current in response to that comparison.

Abstract translation: 通路电路包括耦合在输入节点（接收输入信号）和输出节点（输出输出信号）之间的第一晶体管。 第二晶体管被配置为响应于流过其中的偏置电流产生电压差，其中该电压差被施加在第一晶体管的第一栅极和输出节点之间。 差分放大器用于将输出节点处的电压与参考电压进行比较，并根据该比较产生偏置电流。

公开(公告)号：US08854106B2

公开(公告)日：2014-10-07

申请号：US13925032

申请日：2013-06-24

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Snow Qi ,  Jackson Ding

IPC: H03K5/00 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A level shifting circuit includes a current mirror that generates a first bias current and a second bias current (proportional to the first bias current with a first ratio). A first level shifter is coupled between a first input node (receiving a first input signal) and a first output node coupled to an input of the current mirror. The first level shifter applies a first voltage variation to the first input signal in response to the first bias current. A second level is coupled between a second input node (receiving a second input signal) and a second output node coupled to an output of the current mirror. The second level shifter applies a second voltage variation (associated with the first voltage variation) to the second input signal in response to the second bias current.

Abstract translation: 电平移位电路包括产生第一偏置电流的电流镜和与第一偏置电流成比例的第二偏置电流。 第一电平移位器耦合在第一输入节点（接收第一输入信号）和耦合到当前反射镜的输入端的第一输出节点之间。 第一电平移位器响应于第一偏置电流向第一输入信号施加第一电压变化。 第二级耦合在第二输入节点（接收第二输入信号）和耦合到当前反射镜的输出端的第二输出节点之间。 第二电平移位器响应于第二偏置电流而将第二电压变化（与第一电压变化相关联）施加到第二输入信号。