公开(公告)号：US20040252536A1

公开(公告)日：2004-12-16

申请号：US10862057

申请日：2004-06-04

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C027/00

CPC classification number: G11C15/04

Abstract: A CAM cell with masking made in the form of an integrated circuit, including a first storage cell including a first transistor, first and second inverters in anti-parallel, and a second transistor; a comparison cell, including third and fourth transistors controlling a fifth transistor, connected in series with a sixth inhibiting transistor to a result line; and a second storage cell, including a seventh transistor in series with two inverters in anti-parallel and an eighth transistor, the second storage cell controlling the inhibiting transistor. The first, second, seventh, and eighth transistors may be N-channel transistors, and the third, fourth, fifth, and sixth transistors may be P-channel transistors.

Abstract translation: 具有以集成电路形式形成的掩蔽的CAM单元，包括：第一存储单元，包括第一晶体管，反并联的第一和第二反相器以及第二晶体管; 比较单元，包括控制第五晶体管的第三和第四晶体管，与第六抑制晶体管串联连接到结果行; 以及第二存储单元，其包括与反并联的两个反相器串联的第七晶体管和第八晶体管，所述第二存储单元控制所述抑制晶体管。 第一，第二，第七和第八晶体管可以是N沟道晶体管，并且第三，第四，第五和第六晶体管可以是P沟道晶体管。

公开(公告)号：US20010054913A1

公开(公告)日：2001-12-27

申请号：US09891964

申请日：2001-06-26

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: H03K019/20

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: An electronic circuit with digital output including an auto-stable assembly of latches (1), a control assembly (2), a blowable assembly (3), a logic gate (4) including a first input connected to a common point (14) between the auto-stable assembly (1) and the blowable assembly (3), and a second input connected to the control input (20) of the electronic circuit. A breaker (5) is controlled by the output of the logic gate (4) and arranged between the auto-stable assembly (1) and ground, and an associated process.

Abstract translation: 一种具有数字输出的电子电路，包括闩锁（1），控制组件（2），可吹塑组件（3），连接到公共点（14）的第一输入的逻辑门（4））的自动稳定组件， 在自动稳定组件（1）和可吹塑组件（3）之间，以及连接到电子电路的控制输入（20）的第二输入。 断路器（5）由逻辑门（4）的输出控制并且布置在自动稳定组件（1）和地之间，以及相关联的过程。

公开(公告)号：US20040264228A1

公开(公告)日：2004-12-30

申请号：US10717223

申请日：2003-11-19

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C017/00

CPC classification number: G11C7/067 ,  G11C17/123

Abstract: The invention concerns a ROM circuit (40) comprising columns of storage cells, each column being connected to a bit site (BLi, BLinull1), wherein the columns are arranged in groups of two adjacent columns, each column of a group capable of being selectively activated relative to the other column of the group, thereby enabling the elimination of a connection to the ground of columns and the design of efficient reading amplifiers.

公开(公告)号：US20010055220A1

公开(公告)日：2001-12-27

申请号：US09853254

申请日：2001-05-11

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C011/24 ,  H03H011/26

CPC classification number: G11C11/4099 ,  G11C7/14

Abstract: A voltage regulation device is for a reference cell of a dynamic random access memory arranged in lines and columns and including a plurality of memory cells. The device includes at least one capacitor of a predetermined capacitance which can be discharged during memory access.

Abstract translation: 电压调节装置用于布置成行和列并且包括多个存储单元的动态随机存取存储器的参考单元。 该装置包括至少一个预定电容的电容器，其可以在存储器存取期间被放电。

公开(公告)号：US20030022427A1

公开(公告)日：2003-01-30

申请号：US10186289

申请日：2002-06-27

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant ,  Florent Vautrin

IPC: H01L021/8238

CPC classification number: G11C11/406

Abstract: A device and a method for refreshing the voltage of a circuit line that provides the capability of bringing the circuit line to a ground voltage or to a first voltage. The method provides storing the circuit line voltage in a capacitor; and controlling, by means of the stored voltage, a switch connecting the circuit line to a second voltage of absolute value greater than the first voltage, whereby the circuit line is set to the second voltage if, during the step of storing, the circuit line was at the first voltage.

Abstract translation: 一种用于刷新电路线路的电压的装置和方法，其提供使电路线路接地电压或第一电压的能力。 该方法提供将电路线电压存储在电容器中; 以及通过所存储的电压来控制将所述电路线连接到绝对值大于所述第一电压的第二电压的开关，由此在所述电路线路的存储步骤期间将所述电路线设置为所述第二电压 处于第一电压。

公开(公告)号：US20020009008A1

公开(公告)日：2002-01-24

申请号：US09883697

申请日：2001-06-18

Applicant: STMicroelectronics S.A.

Inventor： Richard Ferrant

IPC: G11C007/00

CPC classification number: G11C11/4094

Abstract: Each memory cell of a memory device is connected to a bit line of a memory array and is associated with a read/rewrite amplifier connected between the bit line and a reference bit line. The bit line and the reference bit line are precharged to a predetermined precharge voltage. The content of a selected memory cell is read and refreshed based upon an associated read/rewrite amplifier. Between the precharging and the reading and refreshing, two capacitors previously charged to a charging voltage greater than the precharge voltage are respectively connected to the bit line and to the reference bit line.

Abstract translation: 存储器件的每个存储器单元连接到存储器阵列的位线，并且与连接在位线和参考位线之间的读取/重写放大器相关联。 位线和参考位线被预充电到预定的预充电电压。 所选择的存储单元的内容基于相关联的读取/重写放大器被读取和刷新。 在预充电和读取和刷新之间，预先充电到大于预充电电压的充电电压的两个电容器分别连接到位线和参考位线。