Abstract:
An electric motor is controlled by means of pulse-width modulated control signal having edge transitions occurring at certain transition count values of the pulses of a clock signal which is frequency-modulated with a step-wise frequency modulation (e.g., SSCG or Spread Spectrum Clock Generation). A frequency unmodulated clock signal is provided having a fixed period indicative of the period of the pulse-width modulated control signals. The transition count values are set as a function of a predicted count value and/or a predicted frequency value for the frequency-modulated clock signal. Prediction occurs as a function of the frequency unmodulated clock signal, so that the transition count values are compensated against the step-wise (e.g., SSCG) frequency modulation.
Abstract:
A driver device for driving a DC motor using PWM modulated drive signals includes comparator circuits for producing digitalized Back-EMF signals having first and second values as a function of the Back-EMF signals being above or below a respective threshold, and an inverter for driving the PWM modulated drive signals in a phased relationship with the digitalized Back-EMF signals. The driver device also includes controller circuits configured for controlling the respective threshold by minimizing the error between a time measured between two consecutive opposed edges of the digitalized Back-EMF signal and half a time measured between two consecutive homologous edges of the digitalized Back-EMF signal.
Abstract:
An electric motor is controlled by means of pulse-width modulated control signal having edge transitions occurring at certain transition count values of the pulses of a clock signal which is frequency-modulated with a step-wise frequency modulation (e.g., SSCG or Spread Spectrum Clock Generation). A frequency unmodulated clock signal is provided having a fixed period indicative of the period of the pulse-width modulated control signals. The transition count values are set as a function of a predicted count value and/or a predicted frequency value for the frequency-modulated clock signal. Prediction occurs as a function of the frequency unmodulated clock signal, so that the transition count values are compensated against the step-wise (e.g., SSCG) frequency modulation.