公开(公告)号：US20040156235A1

公开(公告)日：2004-08-12

申请号：US10719650

申请日：2003-11-21

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Bellini ,  Mauro Sali ,  Alessandro Magnavacca ,  Carlo Lisi

IPC: G11C011/34

CPC classification number: G11C16/26 ,  G11C16/344 ,  G11C2216/22

Abstract: A nonvolatile memory device with simultaneous read/write has a memory array formed by a plurality of cells organized into memory banks, and a plurality of first and second sense amplifiers. The device further has a plurality of R/W selectors associated to respective sets of cells and connecting the cells of the respective sets of cells alternately to the first sense amplifiers and to the second sense amplifiers.

Abstract translation: 具有同时读/写的非易失性存储器件具有由组织到存储体中的多个单元形成的存储器阵列以及多个第一和第二读出放大器。 该装置还具有与相应的单元组相关联的多个R / W选择器，并将各组单元的单元交替地连接到第一读出放大器和第二读出放大器。

公开(公告)号：US20020018390A1

公开(公告)日：2002-02-14

申请号：US09909467

申请日：2001-07-19

Applicant: STMicroelectronics S.r.I.

Inventor： Emanuele Confalonieri ,  Lorenzo Bedarida ,  Mauro Sali ,  Simone Bartoli

IPC: G11C005/14

CPC classification number: G11C16/30

Abstract: A semiconductor memory includes a plurality of memory cells connected to one another to form a matrix of memory cells. A charge pump is connected to the matrix of memory cells. A plurality of controllable connection elements are provided, with each controllable connection element connected between an output terminal of the charge pump and a respective column line. Connected to the output of the charge pump is the series connection of a first element equivalent to a controllable connection element, and a second element equivalent to a memory cell in a predetermined biasing condition. A voltage regulator is connected between the second equivalent element and the input terminal of the charge pump for regulating the output voltage therefrom based upon a voltage present between terminals of the second equivalent element.

公开(公告)号：US20030235097A1

公开(公告)日：2003-12-25

申请号：US10449761

申请日：2003-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Emilio Camerlenghi ,  Paolo Cappelletti ,  Tecla Ghilardi ,  Mauro Sali ,  Giorgio Servalli

IPC: G11C007/00

CPC classification number: G11C29/006 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/5002

Abstract: An integrated non-volatile memory device may include a first matrix of memory cells organized into rows (or word lines) and columns (or bit lines), corresponding row and column decoding circuits, and read, modify and erase circuits for reading and modifying data stored in the memory cells. Furthermore, the memory device may also include a test structure including a second matrix of memory cells smaller than the first. The second memory matrix may include word line couplings each having a different contact to gate distance. That is, each coupling is aligned a different distance from its respective gate than adjacent couplings.

Abstract translation: 集成的非易失性存储器件可以包括组织成行（或字线）和列（或位线），对应的行和列解码电路的存储器单元的第一矩阵，以及用于读取和修改数据的读取，修改和擦除电路 存储在存储单元中。 此外，存储器件还可以包括测试结构，其包括小于第一存储器单元的存储器单元的第二矩阵。 第二存储器矩阵可以包括每个具有与栅极距离的不同接触的字线耦合。 也就是说，每个联轴器与相应的门相比不同于相邻联接器的距离。