公开(公告)号：US20030018861A1

公开(公告)日：2003-01-23

申请号：US10159782

申请日：2002-05-30

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Massimiliano Picca ,  Roberto Ravasio ,  Stefano Zanardi

IPC: G06F012/00

CPC classification number: G06F11/1072 ,  G11C2211/5641

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

Abstract translation: 一种用于存储可配置位数的多电平存储单元中的误差控制的方法。 使用在编码阶段中对由r位数据的k个符号组成的b位二进制字符串进行操作的错误控制代码执行错误控制。 当存储器单元存储数位r的位时，仅与存储在存储单元中的数据位形成数据符号。 当存储器单元存储少于r的位数时，形成数据符号，其中存储在存储单元中的数据位和具有预定逻辑值的rs位，其中存储在存储单元中的数据位 被布置在数据符号的最低有效部分中，并且具有预定逻辑值的rs位被布置在数据符号的最重要部分中。

公开(公告)号：US20040230869A1

公开(公告)日：2004-11-18

申请号：US10805182

申请日：2004-03-19

Applicant: STMicroelectronics S.r.I.

Inventor： Rino Micheloni ,  Roberto Ravasio

IPC: H05K010/00

CPC classification number: G06F11/1068 ,  G06F11/1048

Abstract: An embodiment of the present invention relates to an integrated memory system comprising at least a non-volatile memory and an automatic storage error corrector, and wherein the memory is connected to a controller by means of an interface bus. Advantageously, the system comprises in the memory circuit means, functionally independent, each being responsible for the correction of a predetermined storage error; at least one of said means generating a signal to ask a correction being external to the memory.

Abstract translation: 本发明的实施例涉及至少包括非易失性存储器和自动存储错误校正器的集成存储器系统，并且其中存储器通过接口总线连接到控制器。 有利地，该系统在存储器电路装置中包括功能上独立的，每个都负责校正预定的存储错误; 所述装置中的至少一个产生要求校正在存储器外部的信号。