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Patent Agency Ranking
公开(公告)号：US20210126643A1
公开(公告)日：2021-04-29
申请号：US17078945
申请日：2020-10-23
Applicant: STMicroelectronics S.r.l.
Inventor： Domenico TRIPODI
Abstract: A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.
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公开(公告)号：US20210126627A1
公开(公告)日：2021-04-29
申请号：US17077833
申请日：2020-10-22
Applicant: STMicroelectronics S.r.l.
Inventor： Domenico TRIPODI , Luca GIUSSANI , Simone Ludwig DALLA STELLA
IPC: H03K3/017
Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
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公开(公告)号：US20240297640A1
公开(公告)日：2024-09-05
申请号：US18657642
申请日：2024-05-07
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Domenico TRIPODI , Luca GIUSSANI , Simone Ludwig DALLA STELLA
Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
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公开(公告)号：US20230208404A1
公开(公告)日：2023-06-29
申请号：US18175359
申请日：2023-02-27
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Domenico TRIPODI , Luca GIUSSANI , Simone Ludwig DALLA STELLA
Abstract: A PWM signal generator circuit includes a multiphase clock generator that generates a number n of phase-shifted clock phases having the same clock period and being phase shifted by a time corresponding to a fraction 1/n of the clock period. The PWM signal generator circuit determines for each switch-on duration first and second integer numbers, and for each switch-off duration third and fourth integer numbers. The first integer number is indicative of the integer number of clock periods of the switch-on duration and the second integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-on duration. The third integer number is indicative of the integer number of clock periods of the switch-off duration, and the fourth integer number is indicative of the integer number of the additional fractions 1/n of the clock period of the switch-off duration.
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5.发明申请公开(公告)号：US20220311329A1
公开(公告)日：2022-09-29
申请号：US17695603
申请日：2022-03-15
Applicant: STMicroelectronics S.r.l.
Inventor： Christian Leone SANTORO , Domenico TRIPODI
Abstract: A method of operating an electronic converter is provided in which a switching activity of a switching stage of the electronic converter is active or inactive based on a control signal, and the method includes operating the electronic converter, alternatively, in a first or a second mode. In the first mode, the status signal is initially asserted and is de-asserted in response to an amplitude of the input sensing signal failing to reach a first reference threshold value. In the second mode, the status signal is initially de-asserted and an auxiliary power supply signal is periodically varied with a variation period. After a time interval equal to the variation period, a comparison signal is asserted in response to an amplitude of the sensed signal reaching a second reference threshold value. The status signal is asserted based on conditions of the comparison signal and the periodically varying auxiliary power supply signal.
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