公开(公告)号：US20240389386A1

公开(公告)日：2024-11-21

申请号：US18656470

申请日：2024-05-06

Applicant: Samsung Display Co., Ltd.

Inventor： KYONG-CHOL LEE ,  DAESOO KIM ,  SANGGAB KIM ,  TAESUNG KIM ,  HYUNMIN CHO ,  DAEWON CHOI

IPC: H10K59/121 ,  G09G3/3233 ,  H10K59/12

Abstract: A display device is disclosed that includes a base layer, a light-emitting element, and a pixel circuit. The pixel circuit includes a first transistor, and the first transistor includes a metal oxide semiconductor pattern, a first gate having a plurality of conductive layers, and a gate insulation pattern. The uppermost layer among the plurality of conductive layers is divided into a first part adjacent to a drain region, a second part adjacent to a source region, and a third part between the first part and the second part. An upper surface of each of the first part and the second part may form a step with an upper surface of the third part. A sum of the widths of the upper surfaces of the first part and the second part may be smaller than the width of the upper surface of the third part.

公开(公告)号：US20240074234A1

公开(公告)日：2024-02-29

申请号：US18188952

申请日：2023-03-23

Applicant: Samsung Display Co., LTD.

Inventor： KYONG-CHOL LEE ,  YUNJONG YEO ,  TAESUNG KIM ,  HYUNMIN CHO ,  YEONHONG KIM

IPC: H10K59/121 ,  H10K59/12 ,  H10K71/00 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H10K59/1213 ,  H10K59/1201 ,  H10K71/00 ,  H01L29/7869 ,  H01L29/42384 ,  H01L29/66742

Abstract: A display device includes a first transistor including a first active pattern including a first oxide semiconductor, and a first gate electrode which is on the first active pattern, a second transistor including a second active pattern including a second oxide semiconductor different from the first oxide semiconductor, and a second gate electrode which is on the second active pattern, a first gate insulating pattern between the second active pattern and the second gate electrode, a second gate insulating pattern facing the first gate insulating pattern with the second active pattern therebetween, and a third gate insulating pattern between the first active pattern and the first gate electrode, the third gate insulating pattern directly contacting the first active pattern and the first gate electrode.