公开(公告)号：US20220351672A1

公开(公告)日：2022-11-03

申请号：US17588806

申请日：2022-01-31

Applicant: Samsung Display Co., Ltd.

Inventor： CHANG-SOO LEE ,  BOYONG CHUNG

IPC: G09G3/32

Abstract: A pixel includes: a light emitting element; a first transistor which drives the light emitting element; a second transistor electrically connected between a gate node of the first transistor and a data line; a third transistor electrically connected between a first node of the first transistor and an initialization voltage line; and a storage capacitor electrically connected between the gate node and the first node of the first transistor. Here, upon an operation in a variable frame mode, an initialization voltage is applied to the initialization voltage line, and the initialization voltage has a first voltage level. In addition, in a data writing period during which the storage capacitor is charged with an electric charge, the initialization voltage further includes a pulse voltage such that the initialization voltage has a second voltage level that is greater than the first voltage level.

公开(公告)号：US20240078962A1

公开(公告)日：2024-03-07

申请号：US18143011

申请日：2023-05-03

Applicant: Samsung Display Co., Ltd.

Inventor： HYUK KIM ,  JONGHEE KIM ,  DOO-YOUNG LEE ,  CHANG-SOO LEE ,  SANG-UK LIM ,  BOYONG CHUNG

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2310/0267 ,  G09G2310/08 ,  H01L27/124

Abstract: Provided is a gate driving circuit comprising an N-th stage and an N+1-th stage. The N-th stage outputs an N-th scan gate signal based on an N-th scan clock signal, a voltage of a QN node, and a voltage of a QBN node and to output an N-th carry signal based on an N-th carry clock signal, the voltage of the QN node, and the voltage of the QBN node. The N+1-th stage outputs an N+1-th scan gate signal based on an N+1-th scan clock signal, a voltage of a QN+1 node, and the voltage of the QBN node and an N+1-th carry signal based on an N+1-th carry clock signal, the voltage of the QN+1 node, and the voltage of the QBN node. The N-th stage and the N+1-th stage share an inverting circuit. The inverting circuit controls the QBN node based on a third signal. N is a positive integer.

公开(公告)号：US20190197937A1

公开(公告)日：2019-06-27

申请号：US16231657

申请日：2018-12-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： CHANG-SOO LEE ,  Byoungsun NA

IPC: G09G3/20

Abstract: A display apparatus includes a display panel including a display area and a non-display area, in which an image is displayed in the display area and a peripheral area is disposed adjacent to the display area in the non-display area. The display panel includes a plurality of gate lines extending in a first direction, a plurality of data lines extending a second direction which crosses the first direction, and a plurality of unit pixels which are electrically connected to each of the gate lines and the data lines. A gate driver generates a clock signal, and a gate signal generator receives the clock signal and outputs a generated gate signal to the gate line. A clock line transmits the clock signal to the gate signal generator, and a flexible film disposed adjacent to the gate signal generator in the first direction is connected to the display panel in the peripheral area. At least a portion of the clock line is formed on the flexible film.

公开(公告)号：US20160189655A1

公开(公告)日：2016-06-30

申请号：US14740652

申请日：2015-06-16

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： HAK-MO CHOI ,  HOl-SIK MOON ,  GWANG-HO NAM ,  CHANG-SOO LEE ,  MIN-YUP CHAE

IPC: G09G3/36

CPC classification number: G09G3/3685 ,  G09G3/3614 ,  G09G3/3666 ,  G09G3/3674 ,  G09G2300/0413 ,  G09G2310/0251 ,  G09G2310/08 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2320/0252 ,  G09G2320/0673

Abstract: A method of driving a display panel is provided. The display panel includes first through n-th gate lines and a plurality of pixels each connected to one of the first through n-th gate lines (where n is a natural number). The method includes charging pixels connected to the n-th gate line with first data voltages corresponding to a first frame image during a first period, charging pixels connected to the first gate line with the first data voltages during the first period, charging the pixels connected to the first gate line with second data voltages corresponding to a second frame image during a second period subsequent to the first period, and charging pixels connected to the second gate line with the second data voltages during the second period.

Abstract translation: 提供了一种驱动显示面板的方法。 显示面板包括第一至第n栅极线和多个像素，每个像素连接到第一至第n栅极线之一（其中n为自然数）。 该方法包括：在第一周期期间，将与第n栅极线连接的第一数据电压的第一数据电压充电到第一时段中，对与第一栅极线连接的第一数据电压进行充电，对连接的像素进行充电 在所述第一周期之后的第二周期期间具有与第二帧图像对应的第二数据电压的第一栅极线，以及在所述第二周期期间以与所述第二数据电压连接的所述第二栅极线的像素进行充电。