Display device
    1.
    发明授权

    公开(公告)号:US11569328B2

    公开(公告)日:2023-01-31

    申请号:US17223984

    申请日:2021-04-06

    Abstract: A display device includes a substrate, a corrosion prevention layer on the substrate and including an inorganic material, a first conductive layer on the corrosion prevention layer and including aluminum or an aluminum alloy, a first insulating film on the first conductive layer, a semiconductor layer on the first insulating film and including a channel region of a transistor, a second insulating film on the semiconductor layer, and a second conductive layer on the second insulating film and including a barrier layer, which includes titanium, and a main conductive layer, which includes aluminum or an aluminum alloy, wherein the semiconductor layer includes an oxide semiconductor, and the barrier layer is between the semiconductor layer and the main conductive layer and overlaps the channel region of the transistor.

    Thin film transistor array panel with channel-shaping etching stopper

    公开(公告)号:US10243008B2

    公开(公告)日:2019-03-26

    申请号:US15602018

    申请日:2017-05-22

    Inventor: Eun Hyun Kim

    Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

    Thin film transistor array panel comprising etch stopper for shaping a channel

    公开(公告)号:US09659972B2

    公开(公告)日:2017-05-23

    申请号:US14466944

    申请日:2014-08-22

    Inventor: Eun Hyun Kim

    CPC classification number: H01L27/124 H01L27/1248 H01L29/41733

    Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

    THIN FILM TRANSISTOR ARRAY PANEL
    4.
    发明申请

    公开(公告)号:US20170256567A1

    公开(公告)日:2017-09-07

    申请号:US15602018

    申请日:2017-05-22

    Inventor: Eun Hyun Kim

    CPC classification number: H01L27/124 H01L27/1248 H01L29/41733

    Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

    THIN FILM TRANSISTOR ARRAY PANEL
    7.
    发明申请
    THIN FILM TRANSISTOR ARRAY PANEL 有权
    薄膜晶体管阵列

    公开(公告)号:US20150236044A1

    公开(公告)日:2015-08-20

    申请号:US14466944

    申请日:2014-08-22

    Inventor: Eun Hyun Kim

    CPC classification number: H01L27/124 H01L27/1248 H01L29/41733

    Abstract: A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A.

    Abstract translation: 薄膜晶体管阵列面板包括:基板; 栅极线在衬底上,每条栅极线包括栅电极; 衬底上的半导体层; 半导体层上的蚀刻停止层; 基板上的数据布线层,包括数据线,与数据线连接的源电极和漏电极; 以及覆盖源电极,漏电极和蚀刻停止器的钝化层,其中蚀刻停止器包括在源电极和漏电极之间的防蚀刻部分,其中,上侧和下侧之间的最短距离A 防蚀部和半导体层重叠的重叠区域由平面图中的直线表示,半导体层的沟道部的宽度大于最短距离A.

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